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1gb ddr3l C as4c128m8d3l confidential 1 rev. 2 . 0 a ug . / 20 1 4 revision history as4c 128 m8d3 l - 78 - ball fbga package revision details date rev 1.0 preliminary datasheet april 201 4 rev 2 .0 a dded "backward compatible to vdd & vddq = 1.5v +/ - 0.075v" - page 2 august 2014 updated table 12 . recommended dc operating conditions C page 21 added c l=5 & cl=6 to table 18 C page 26
1gb ddr3l C as4c128m8d3l confidential 2 rev. 2 . 0 a ug . / 20 1 4 128 m x 8 bit ddr3l synchronous dram (sdram) confidential advanced (rev . 2 . 0 , a ug . / 20 1 4 ) features ? jedec standard compliant ? power supplies: v dd & v ddq = +1. 3 5 v ? backward c ompatible : v dd & v ddq = 1.5v +/ - 0.075v ? ? ? f ully synchronous operation ? ? ? ? ? ? ? ? ? ? ? ? ? 8192 refresh cycles / 64ms - average refresh period 7.8 s @ - 4 0 Q tc Q +85 3.9 s @ +85 tc Q +95 ? ? ? ? ? ? 78 - ball 8 x 1 0. 5 x 1.2mm fbga p ackage - pb and halogen free overview the 1 gb double - data - rate - 3 (ddr3l) drams is double data rate architecture to achieve h igh - speed operation. it is internally configured as an eight bank dram. the 1 gb chip is organized as 16 mbit x 8 i/os x 8 bank devices. these synchronous devices achieve high speed double - data - rate transfer rates of up to 1 600 mb/sec/pin for general applica tions. the chip is designed to comply with all key ddr3l dram key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck r ising and ck# falling). all i/os are synchronized with differential dqs pair in a source synchronous fashion. these devices operate with a single 1. 3 5v - 0.0 67 v /+0.1v power supply and are available in bga packages. table 1 . speed grade i nformation speed grade clock frequency cas latency t rcd (ns) t rp (ns) ddr3l - 1600 800 mhz 11 13.75 13.75 table 2. ordering information product part no org temperature package as4c128m8d3l - 12bcn 128m x 8 commercial (extended) 0c to 95c 78 - ball fbga as4c128m8d3l - 12b in 128m x 8 industrial - 40c to 95c (extended) 78 - ball fbga
1gb ddr3l C as4c128m8d3l confidential 3 rev. 2 . 0 a ug . / 20 1 4 figure 1. ball assignment (fbga top view) a b c d e 1 2 3 7 8 9 v s s v d d v s s v s s q v d d q d q 2 v s s q d q 6 v r e f d q v d d q n c d q 0 d q s d q s # d q 4 . t d q s # v s s d m / t d q s v s s q d q 1 d q 3 v d d v s s d q 7 d q 5 v d d v d d q v s s q v s s q v d d q f n c v s s r a s # c k v s s n c g o d t v d d c a s # c k # v d d c k e h n c c s # w e # a 1 0 / a p z q n c j v s s b a 0 b a 2 n c v r e f c a v s s k a 3 a 0 a 1 2 / b c # b a 1 v d d l v s s a 5 a 2 a 1 a 4 m a 7 a 9 a 1 1 a 6 v d d n v s s r e s e t # a 1 3 n c a 8 v d d v d d v s s v s s
1gb ddr3l C as4c128m8d3l confidential 4 rev. 2 . 0 a ug . / 20 1 4 figure 2 . block diagram c k # c k e c s # r a s # c a s # w e # d l l c l o c k b u f f e r c o m m a n d d e c o d e r c o l u m n c o u n t e r a d d r e s s b u f f e r a 1 0 / a p a 0 - a 9 a 1 1 a 1 3 b a 0 - b a 2 c k d q s d q s # d q b u f f e r d m d q 7 d q 0 ~ o d t c o n t r o l s i g n a l g e n e r a t o r r e f r e s h c o u n t e r d a t a s t r o b e b u f f e r m o d e r e g i s t e r z q c a l z q c s z q c l r e s e t # a 1 2 / b c # v s s q r z q 1 6 m x 8 c e l l a r r a y ( b a n k # 0 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 1 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 2 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 3 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 4 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 5 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 6 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 7 ) r o w d e c o d e r c o l u m n d e c o d e r t d q s t d q s #
1gb ddr3l C as4c128m8d3l confidential 5 rev. 2 . 0 a ug . / 20 1 4 figure 3. state dia gr am this simplified state diagram is inte nded to provide an overview of the possible state transitions and the c ommands to control them. in particular, situations involving more than one bank, the enabling or disabling of on - die termination, and some other events are not captured in full detail . p o w e r o n a u t o m a t i c s e q u e n c e c o m m a n d s e q u e n c e p o w e r a p p l i e d r e s e t p r o c e d u r e i n i t i a l i z a t i o n r e s e t f r o m a n y s t a t e z q c l z q c a l i b r a t i o n i d l e s e l f r e f r e s h r e f r e s h i n g s r e m r s r e f s r x z q c l , z q c s a c t i v e p o w e r d o w n a c t i v a t i n g p r e c h a r g e p o w e r d o w n p d e p d x a c t b a n k a c t i v a t i n g w r i t i n g w r i t i n g r e a d i n g p r e c h a r g i n g p d x p d e r e a d r e a d r e a d a r e a d a w r i t e w r i t e r e a d w r i t e w r i t e a r e a d a p r e , p r e a w r i t e a w r i t e a p r e , p r e a p r e , p r e a a c t = a c t i v e p r e = p r e c h a r g e r e f = r e f r e s h p r e a = p r e c h a r g e a l l m r s = m o d e r e g i s t e r s e t z q c l = z q c a l i b r a t i o n l o n g r e a d = r d , r d s 4 , r d s 8 r e a d a = r d a , r d a s 4 , r d a s 8 w r i t e = w r , w r s 4 , w r s 8 w r i t e a = w r a , w r a s 4 , w r a s 8 r e s e t = s t a r t r e s e t p r o c e d u r e z q c s = z q c a l i b r a t i o n s h o r t p d e = e n t e r p o w e r - d o w n p d x = e x i t p o w e r - d o w n s r e = s e l f - r e f r e s h e n t r y s r x = s e l f - r e f r e s h e x i t m p r = m u l t i - p u r p o s e r e g i s t e r r e a d i n g m r s , m p r , w r i t e l e v e l i n g
1gb ddr3l C as4c128m8d3l confidential 6 rev. 2 . 0 a ug . / 20 1 4 ball descriptions table 3 . ball descriptions symbol type description ck, ck # input differential clock: ck and ck # are driven by the system clock. all sdram input signals are sampled on the crossing of po sitive edge of ck an d negative edge of ck #. output ( r ead) data is referenced to the crossings of ck and ck # ( both directions of crossing). cke input clock enable: cke activates ( high) and deactivates ( low ) the ck signal. if cke goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is froze n as long as the cke remains low . when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. b a 0 - b a 2 input bank address : b a 0 - b a 2 define to which bank the bankactiv ate, read, write, or bankprecharge command is being applied. a0 - a1 3 input address inputs: a0 - a1 3 are sampled during the bankactivate command (row address a0 - a1 3 ) and read/write command (co lumn address a0 - a 9 with a10 defining auto precharge ). a10/ap input auto - precharge: a10 is sampled during read/write commands to determine whether autoprecharge should be performed to the accessed bank after the read/write operation. (high: autoprecharge; low: no autoprecharge). a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). a12/ bc# input burst chop: a12/ b c # is sampled during read and write commands to determine if burst chop (on the fly) will be performed. (high - no burst chop; low - burst chopped). cs # input chip select: cs # enables (sampled low) and disables (sampled high) the command decoder . all commands are masked when cs # is sampled high. it is considered part of the command code. ras # input row address strobe: the ras # signal defines the operation co mmands in conjunction with the cas # and we # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . when ras # and cs # are asserted "l ow" and cas # is asserted "high," either the bankactivate command or the precha rge command is selected by the we # signal. when the we # is asserted "high," the bankactivate command is selected and the bank designated by b a is turned on to the active state. w hen the we # is asserted "low," the precharge command is selected and the bank designated by b a is switched to the idle state after the precharge operation. cas # input column address strobe: the cas # signal defines the operation commands in conjunction wit h the ras # and we # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . when ras # is held "high" and cs # is asserted "low," the column access is started by asserting cas # "low." then, the read or write co mmand is selecte d by asserting we # high " or low ". we # input write enable: the we # signal defines the operation commands in conjunction with the ras # and cas # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . the we # input is used to select the bankactivate or precharge command and read or write command. dqs, dqs # input / output bidirectional data strobe: specifies timing for input and output data. read data strobe is edge triggered. write data strobe provides a setup and hold ti me for data and dm. the data strobes dos is paired with dqs# to provide differential pair signaling to the system during both reads and writes. t dqs t dqs # output termination d ata s trobe: when tdqs is enabled, dm is disabled, and the tdqs and tdqs# balls p rovide termination resistance .
1gb ddr3l C as4c128m8d3l confidential 7 rev. 2 . 0 a ug . / 20 1 4 dm input data input mask: input data is masked when dm is sampled high during a write cycle. dm has an optional use as tdqs on the x8 . dq0 C dq 7 input / output data i/o: the dq0 - dq 7 input and output data are synchronized w ith positive and negative edges of dqs and dqs #. the i/os are byte - maskable during writes. odt input on die termination: odt (registered high) enables termination resistance internal t o the ddr3l sdram. when enabled, odt is applied to each dq, dqs, dqs# , dm/tdqs and tdqs# signal . (when tdqs is enabled via mode register a11=1 in mr1) the odt pin will be ignored if mode - registers, mr1and mr2, are programmed to disable rtt. reset # input active low asynchronous reset: reset is active when reset # is low, and inactive when reset# is high. reset # must be high during normal operation. reset# is a cmos rail to rail signal with dc high and low at 80% and 20% of vdd v dd supply power supply: +1.35v - 0.067v/ +0.1v v ss supply ground v ddq supply dq power: +1.35v - 0. 067v/ +0.1v v ssq supply dq ground v ref ca supply reference voltage for ca v ref dq supply reference voltage for dq zq supply reference pin for zq calibration. nc - no connect: these pins should be left unconnected.
1gb ddr3l C as4c128m8d3l confidential 8 rev. 2 . 0 a ug . / 20 1 4 opera tion mode truth table table 4 . truth table (note (1), (2 )) command state cke n - 1 ( 3 ) cke n dm b a 0 - 2 a10 /ap a0 - 9, 11 , 13 a12/bc# cs # ras # cas # we # bankactivate idle ( 4 ) h h x v row address l l h h single bank precharge any h h x v l v v l l h l all banks pre charge any h h x v h v v l l h l write (fixed bl8 or bc4) active ( 4 ) h h x v l v v l h l l write (bc4, on the fly) active ( 4 ) h h x v l v l l h l l write (bl8, on the fly) active ( 4 ) h h x v l v h l h l l write with autoprecharge (fixed bl8 or bc4) activ e ( 4 ) h h x v h v v l h l l write with autoprecharge (bc4, on the fly) active ( 4 ) h h x v h v l l h l l write with autoprecharge (bl8, on the fly) active ( 4 ) h h x v h v h l h l l read (fixed bl8 or bc4) active ( 4 ) h h x v l v v l h l h read (bc4, on the fly) active ( 4 ) h h x v l v l l h l h read (bl8, on the fly) active ( 4 ) h h x v l v h l h l h read with autoprecharge (fixed bl8 or bc4) active ( 4 ) h h x v h v v l h l h read with autoprecharge (bc4, on the fly) active ( 4 ) h h x v h v l l h l h read with autoprecharge (bl8, on the fly) active ( 4 ) h h x v h v h l h l h ( extended ) mode register set idle h h x v op code l l l l no - operation any h h x v v v v l h h h device deselect any h h x x x x x h x x x burst stop active ( 5 ) h x x x x x x l h h l refre sh idle h h x v v v v l l l h selfrefresh entry idle h l x v v v v l l l h selfrefresh exit idle l h x x x x x h x x x v v v v l h h h power down mode entry idle h l x x x x x h x x x v v v v l h h h power down mode exit any l h x x x x x h x x x v v v v l h h h data in put mask disable active h x l x x x x x x x x data input mask enable ( 6 ) active h x h x x x x x x x x zq calibration long idle h h x x h x x l h h l zq calibration short idle h h x x l x x l h h l n ote 1: v=valid da ta, x=don't care, l=low level, h=high level note 2: cken signal is input level when commands are provided. note 3 : cken - 1 signal is input level one clock cycle before the commands are provided. note 4: these are states of bank designated by b a signal. note 5: device state is 4 , and 8 burst operation. note 6: ldm and udm can be enable d respectively.
1gb ddr3l C as4c128m8d3l confidential 9 rev. 2 . 0 a ug . / 20 1 4 functional description the ddr3l sdram is a high - speed dynamic random access memory internally configured as an eight - bank dram. the ddr3l sdram uses an 8n pre fetch architecture to achieve high speed operation. the 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write operation for the ddr3l sdram consists of a single 8n - bit wide, four clock data transfer at the internal dram core and two corresponding n - bit wide, one - half clock cycle data transfers at the i/o pins. read and write operation to the ddr3l sdram are burst oriented, start at a selected location, and continue for a burst length of eight or a chopped burst of four in a programmed sequence. operation begins with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active comman d are used to select the bank and row to be activated (ba0 - ba2 select the bank; a0 - a1 3 select the row). the address bit registered coincident with the read or write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via a10), and select bc4 or bl8 mode on the fly (via a12) if enabled in the mode register. prior to normal operation, the ddr3l sdram must be powered up and initialized in a predefined manner. the following sections provide detailed information covering device reset and initialization, register definition, command descriptions and device operation. figure 4 . reset and initialization sequence at power - on ramping c k # v d d q t b t c t d t e t f t g t h t i t j t a r e s e t # c k t c k s r x t k t = 2 0 0 s t = 5 0 0 s t d l l k t x p r t m r d t m r d t m r d t m o d t z q i n i t m r s n o t e 1 m r s m r s m r s z q c l n o t e 1 v a l i d m r 3 m r 2 m r 1 m r 0 v a l i d v a l i d v d d c k e b a o d t r t t t m i n = 1 0 n s t i s t i s t i s t i s s t a t i c l o w i n c a s e r t t _ n o m i s e n a b l e d a t t i m e t g , o t h e r w i s e s t a t i c h i g h o r l o w d o n ' t c a r e t i m e b r e a k n o t e 1 . f r o m t i m e p o i n t c o m m a n d
1gb ddr3l C as4c128m8d3l confidential 10 rev. 2 . 0 a ug . / 20 1 4 ? power - up and in itialization the following sequence is required for power up and initialization . 1. apply power ( reset# is recommended to be maintained below 0.2 x vdd, all other inputs may be undefined). reset# needs t o be maintained for minimum 200 u s with stable power . cke is pulled low anytime before reset# being de - asserted (min. time 10ns). the power voltage ramp time between 300mv to vddmin must be no greater than 200ms; and during the ramp, vdd>vddq and (vdd - vddq) <0.3 volts. - vdd and vddq are driven from a sin gle power converter output, and - the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. in addition, vtt is limited to 0.95v max once power ramp is finished, and - vref tracks vddq/2. or - apply vdd without any slope reversal before or at the same time as vddq. - apply vddq without any slope reversal before or at the same time as vtt & vref. - the voltage levels on all pins oth er than vdd, vddq, vss, vssq must be less than or equal to vddq an d vdd on one side and must be larger than or equal to vssq and vss on the other side. 2. after reset# is de - asserted, wait for another 500us until cke become active. during this time, the dr am will start internal state initialization; this will be done independently of external clocks. 3. clock (ck, ck# ) need to be started and stabilized for at least 10ns or 5tck (which is larger) before cke goes active. since cke is a synchronous signal, the corresponding set up time to clock (tis) must be meeting. also a nop or deselect command must be registered (with tis set up time to clock) before cke goes active. once the cke registered high after reset, cke needs to be continuously registered high until the initialization sequence is finished, including expiration of tdllk and tzqinit. 4. the ddr3l dram will keep its on - die termination in high impedance state as long as reset# is asserted. further, the dram keeps its on - die termination in high imped ance state after reset# de assertion until cke is registered high. the odt input signal may be in undefined state until tis before cke is registered high. when cke is registered high, the odt input signal may be statically held at either low or high. if rtt _nom is to be enabled in mr1, the odt input signal must be statically held low. in all cases, the odt input signal remains static until the power up initialization sequence is finished, including the expiration of tdllk and tzqinit. 5. after cke being regi stered high, wait minimum of reset cke exit time, txpr, before issuing the first mrs command to load mode register. ( txpr =max (txs, 5tck) ) 6. issue mrs command to load mr2 with all application settings. (to issue mrs command for mr2, provide low to ba0 an d ba2, high to ba1) 7. issue mrs c ommand to load mr3 with all application settings. (to issue mrs command for mr3, provide low to ba2, high to ba0 and ba1) 8. issue mrs c ommand to load mr1 with all application settings and dll enabled. (to issue dll enable command, provide low to a0, high to ba0 and low to ba1 and ba2) 9. issue mrs command to load mr0 with all application settings and dll reset. (to issue dll r eset command p rovide high to a8 and low to ba0 - ba2) 10. issue zqcl command to starting zq calibration. 11. wait for both tdllk and tzqinit completed. 12. the ddr3l sdram is now ready for normal operation.
1gb ddr3l C as4c128m8d3l confidential 11 rev. 2 . 0 a ug . / 20 1 4 ? reset procedure at stable power the following sequence is required for reset at no power interruption initializatio n. 1. asserted reset below 0.2*vdd anytime when reset is needed (all other inputs may be undefined). reset needs to be maintained for minimum 100ns. cke is pulled low before reset bein g de - asserted (min. time 10ns). 2. follow power - up initialization sequ ence step 2 to 11. 3. the reset s equence is now completed. ddr3l sdram is ready for normal operation. figure 5 . reset procedure at power stable condition c k # v d d q t b t c t d t e t f t g t h t i t j t a r e s e t # c k t c k s r x t k t = 1 0 0 n s t = 5 0 0 s t d l l k t x p r t m r d t m r d t m r d t m o d t z q i n i t m r s n o t e 1 m r s m r s m r s z q c l n o t e 1 v a l i d m r 3 m r 2 m r 1 m r 0 v a l i d v a l i d v d d c o m m a n d c k e b a o d t r t t t i s t i s t i s t i s s t a t i c l o w i n c a s e r t t _ n o m i s e n a b l e d a t t i m e t g , o t h e r w i s e s t a t i c h i g h o r l o w d o n ' t c a r e t i m e b r e a k n o t e 1 . f r o m t i m e p o i n t t m i n = 1 0 n s
1gb ddr3l C as4c128m8d3l confidential 12 rev. 2 . 0 a ug . / 20 1 4 register definition ? programming the mode registers for application flexibility, various functions, features, and modes are programmable in four mode registers, provided by the ddr3l sdram, as user defined variables and they must be programmed via a mode register set (mrs) command. as the default values of the mode regist ers are not defined, contents of mode registers must be fully initialized and/or re - initialized, i.e. , written, after power up and/or reset for proper operation. also the contents of the mode registers can be altered by re - executing the mrs command during normal operation. when programming the mode registers, even if the user chooses to modify only a sub - set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs command is issued. mrs command and dll reset do not affect array contents, which mean these commands can be executed any time after power - up without affecting the array contents. the mode register set command cycle time, tmrd is required to complete the write operation to the mode register and is the m inimum time required between two mrs commands shown in figure 6 . figure 6 . tmrd timing the mrs command to non - mrs command delay, tmod, is require for the dram to update the features except dll reset, and is the minimum time required from an mrs command to a non - mrs command excluding nop and des shown in figure 7 . t 1 t 2 t a 0 t a 1 t b 0 t b 1 t b 2 t c 0 t c 1 t 0 t c 2 v a l i d t m r d o d t l o f f + 1 d o n ' t c a r e t i m e b r e a k v a l i d v a l i d v a l i d m r s n o p / d e s n o p / d e s m r s n o p / d e s n o p / d e s v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d o l d s e t t i n g s u p d a t i n g s e t t i n g s v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d t m o d n e w s e t t i n g s r t t _ n o m e n a b l e d p r i o r a n d / o r a f t e r m r s c o m m a n d r t t _ n o m d i s a b l e d p r i o r a n d a f t e r m r s c o m m a n d c k # a d d r e s s c k c o m m a n d c k e s e t t i n g s o d t o d t
1gb ddr3l C as4c128m8d3l confidential 13 rev. 2 . 0 a ug . / 20 1 4 figure 7 . tmod timing the mode register contents can be changed using the same command and timing requirements during normal opera tion as long as the dram is in idle state, i.e. , all banks are in the precharged state with trp satisfied, all data bursts are completed and cke is high prior to writing into the mode register. the mode registers are divided into various fields depending o n the functionality and/or modes. c k # t 1 t 2 t a 0 t a 1 t a 2 t a 3 t a 4 t b 0 t b 1 t 0 a d d r e s s c k t b 2 v a l i d c o m m a n d c k e s e t t i n g s o d t o d t o d t l o f f + 1 d o n ' t c a r e t i m e b r e a k v a l i d v a l i d v a l i d m r s n o p / d e s n o p / d e s n o p / d e s n o p / d e s n o p / d e s v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d o l d s e t t i n g s u p d a t i n g s e t t i n g s v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d t m o d n e w s e t t i n g s r t t _ n o m e n a b l e d p r i o r a n d / o r a f t e r m r s c o m m a n d r t t _ n o m d i s a b l e d p r i o r a n d a f t e r m r s c o m m a n d
1gb ddr3l C as4c128m8d3l confidential 14 rev. 2 . 0 a ug . / 20 1 4 ? mode register mr0 the mode - register mr0 stores data for controlling various operating modes of ddr3l sdram. it controls burst length, read burst type, cas latency, test mode, dll reset, wr, and dll control for prechar ge power - down, which include various vendor specific options to make ddr3l dram useful for various applications. the mode register is written by asserting low on cs#, ras#, cas#, we#, ba0, ba1, and ba2, while controlling the states of address pins accordin g to the following figure. table 5. mode register bitmap b a2 ba1 b a0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 0 0 0 *1 ppd wr dll tm cas latency rbt 0 *1 bl mode register (0) ba1 ba0 mrs mode a 7 mode a3 read burst type a1 a0 bl 0 0 mr0 0 normal 0 nibble sequential 0 0 8 (fixed) 0 1 mr1 1 test 1 interleave 0 1 bc4 or 8 (on the fly) 1 0 mr2 1 0 bc4 (fixed) 1 1 mr3 1 1 reserved a11 a10 a9 wr (cycles) a6 a5 a4 c as latency 0 0 0 reserved 0 0 1 5 *2 0 0 0 reserved 0 1 0 6 *2 0 0 1 5 0 1 1 7 *2 0 1 0 6 1 0 0 8 *2 0 1 1 7 1 0 1 10 *2 1 0 0 8 1 1 0 12 *2 1 0 1 9 1 1 1 14 *2 1 1 0 10 1 1 1 11 a12 dll control for precharge pd 0 slow exit (dll off) a8 dll reset 1 fast exit (dll on) 0 no 1 yes note 1 : r eserved for future use and must be set to 0 when programming the mr. note 2: wr (write recovery for autoprecharge) min in clock cycles is calcu lated by dividing twr ( ns) by tck ( ns) and rounding up to the next integer wr min [cycles] =roundup (twr / tck). the value in the mode register must be programmed to be equal or larger than wrmin. the programmed wr value is used with trp to d etermine tdal.
1gb ddr3l C as4c128m8d3l confidential 15 rev. 2 . 0 a ug . / 20 1 4 - burst length, type, and order accesses within a given burst may be programmed to sequential or interleaved order. the burst type is selected via bit a3 as shown in the mr0 definition as above figure. the ordering of access within a burs t is determined by the burst length, burst type, and the starting column address. the burst length is defined by bits a0 - a1. burst lengths options include fix bc4, fixed bl8, and on the fly which allow bc4 or bl8 to be selected coincident with the registra tion of a read or write command via a12/ bc# table 6. burst type and burst order burst length read write starting column address sequential a3=0 interleave a3=1 note a2 a1 a0 4 chop read 0 0 0 0, 1, 2, 3, t, t, t, t 0, 1, 2, 3, t, t, t, t 1, 2, 3 0 0 1 1, 2, 3, 0, t, t, t, t 1, 0, 3, 2, t, t, t, t 0 1 0 2, 3, 0, 1, t, t, t, t 2, 3, 0, 1, t, t, t, t 0 1 1 3, 0, 1, 2, t, t, t, t 3, 2, 1, 0, t, t, t, t 1 0 0 4, 5, 6, 7, t, t, t, t 4, 5, 6, 7, t, t, t, t 1 0 1 5, 6, 7, 4, t, t, t, t 5, 4, 7, 6, t, t, t, t 1 1 0 6, 7, 4, 5, t, t, t, t 6, 7, 4, 5, t, t, t, t 1 1 1 7, 4, 5, 6, t, t, t, t 7, 6, 5, 4, t, t, t, t write 0 v v 0, 1, 2, 3, x, x, x, x 0, 1, 2, 3, x, x, x, x 1, 2, 4, 5 1 v v 4, 5, 6, 7, x, x, x, x 4, 5, 6, 7, x, x, x, x 8 read 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 2 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6 , 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 write v v v 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 2, 4 note 1 : in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock cycles earlier than for the bl8 mode. this means that the starting point for twr and twtr will be pulled in by two clocks. in c ase of burst length being selected on - the - fly via a12/bc#, the internal write operation starts at the same point in time like a burst of 8 write operation. this means that during on - the - fly control, the starting point for twr and twtr will not be pulled in by two clocks. note 2: 0 ~ 7 bit number is value of ca[2:0] that causes this bit to be the first read during a burst. note 3: t: output driver for data and strobes are in high impedance . note 4: v: a valid logic level (0 or 1), but respective buffer inpu t ignores level on input pins. note 5: x: dont care. - cas latency the cas latency is defined by mr0 (bit a 2, a4 ~a 6 ) as shown in the mr0 definition figure. cas latency is the delay, in clock cycles, between the internal read command and the availability of the first bit of output data. ddr3l sdram does not su pport any half clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. - test mode the normal operating mode is selected by mr0 (bit7=0) and all other bits set to the desired values shown in the mr0 definition figure. programming bit a7 to a 1 places the ddr3l sdram into a test mode that is only used by the dram manufacturer and should not be used. no operations or functionality is guaran teed if a7=1. - dll reset the dll reset bit is self - clearing, meaning it returns back to the value of 0 after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. anytime the dll reset function is us ed, tdllk must be met before any functions that require the dll can be used (i.e. read commands or odt synchronous operations.)
1gb ddr3l C as4c128m8d3l confidential 16 rev. 2 . 0 a ug . / 20 1 4 - write recovery the programmed wr value mr0 (bits a9, a10, and a11) is used for the auto precharge feature along with trp to d etermine tdal . wr (write recovery for auto - precharge) min in clock cycles is calculated by dividing twr (ns) by tck (ns) and rounding up to the next integer: wr min [cycles] = roundup (twr [ns]/tck [ns]). the wr must be programmed to be equal or larger tha n twr (min). - precharge pd dll mr0 (bit a12) is used to select the dll usage during precharge power - down mode. when mr0 (a12=0), or slow - exit, the dll is frozen after entering precharge power - down (for potential power savings) and upon exit requires tx pdll to be met prior to the next valid command. when mr0 (a12=1), or fast - exit, the dll is maintained after entering precharge power - down and upon exiting power - down requires txp to be met prior to the next valid command. ? mode register mr1 the mode reg ister mr1 stores the data for enabling or disabling the dll, output strength, rtt_nom impedance, additive latency, write leveling enable , tdqs enable and qoff. the mode register 1 is written by asserting low on cs# , ras# , cas# , we#, high on ba0 and low on ba1 and ba2, while controlling the states of address pins according to the following figure. table 7 . extended mode register emr (1) bitmap b a2 ba1 b a0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 0 1 0 *1 qoff tdqs 0 *1 rtt_nom 0 *1 level rtt_nom d.i.c al rtt_nom d.i.c dll mode register (1) ba1 ba0 mrs mode a4 a3 additive latency a0 dll enable 0 0 mr0 0 0 0 (al disabled) 0 enable 0 1 mr1 0 1 cl C disable 1 0 mr 2 1 0 cl C a12 qoff *2 a 9 a6 a2 rtt_nom *3 0 output buffer enabled 1 o utput buffer disabled 0 0 0 rtt_nom disabled 0 0 1 rzq/4 a11 tdqs a7 write leveling enable 0 1 0 rzq/2 0 disable 0 disabled 0 1 1 rzq/6 1 enable 1 enabled 1 0 0 rzq/12 *4 note: rzq = 240 1 0 1 rzq/8 *4 a5 a1 output driver impedance control 1 1 0 reserved 0 0 rzq/6 1 1 1 reserved 0 1 rzq/7 note: rzq = 240 1 0 reserved 1 1 reserved note 1 : reserved for future use and must be set to 0 when programming the mr . note 2: outputs disabled - dqs, dqss, dqs#s. note 3: in write leveling mode (mr1 [bit7] = 1) with mr1 [bit12] =1, all rtt_nom s ettings are allowed; in write leveling mode (mr1 [bit7] = 1) with mr1 [bit12]=0, only rtt_nom settings of rzq/2, rzq/4 and rzq /6 are allowed. note 4: if rtt_nom is used during writes, only the values rzq/2, rzq/4 and rzq/6 are allowed.
1gb ddr3l C as4c128m8d3l confidential 17 rev. 2 . 0 a ug . / 20 1 4 - dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to n ormal operation after having the dll disabled. during normal operation (dll - on) with mr1 (a0=0), the dll is automatically disabled when entering self - refresh operation and is automatically re - enable upon exit of self - refresh operation. any time the dll is enabled and subsequently reset, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the tdqsck, taon, or taof parameters. during tdllk, cke must continuously be registered high. ddr3l sdram does not require dll for any write operation, expect when rtt_wr is enabled and the dll is required for proper odt operation. for more detailed information on dll disable operation are described in dll - off mode. the direct odt feature is not supported during dll - off mode. the on - die termination resistors must be disabled by continuously registering the odt pin low and/or by programming t he rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2 {a10, a9} = {0, 0}, to disable dynamic odt externally - ou tput driver impedance control the outpu t driver impedance of the ddr3l sdram device is selected by mr1 (bit a1 and a5) as shown in mr1 definition figure. - odt rtt values ddr3l sdram is capable of providing two different termination values (rtt_nom and rt t_wr). the nominal termination value rtt_nom is programmable in mr1. a separate value (rtt_wr) may be programmable in mr2 to enable a unique rtt value when odt is enabled during writes. the rtt_wr value can be applied during writes even when rtt_nom is dis abled. - additive latency (al) additive latency (al) operation is supported to make command and data bus efficient for sustainable bandwidth in ddr3l sdram. in this operation, the ddr3l sdram allows a read or write command (either with or without auto - pre charge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. a summary of the al register options are shown in mr. - write leveling for better signal integrity, ddr3l memory module adopted fly - by topology for the c ommands, addresses, control signals, and clocks. the fly - by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every dram on dimm. it makes difficult for the control ler to maintain tdqss, tdss, and tdsh specification. therefore, the controller should support write leveling in ddr3l sdram to compensate for skew. - output disable the ddr3l sdram outputs maybe enable/disabled by mr1 (bit 12) as shown in mr1 definition . when this feature is enabled (a12=1) all output pins (dqs, dqs, dqs# , etc.) are disconnected from the device removing any loading of the output drivers. this feature may be useful when measuring modules power for example. for normal operation a12 should be set to 0. - tdqs enable tdqs (termination data strobe) is a feature of ddr3l sdram that provides additional termination resistance outputs that may be useful in some system configurations. in contrast to the rdqs function of ddr2 sdram, tdqs provides the termination resistance function only. the data strobe function of rdqs is not provided by tdqs. the tdqs and dm functions share the same pin. when the tdqs function is enabled via the mode register, the dm function is not supported. when the tdqs func tion is disabled, the dm function is provided and the tdqs# pin is not used. the tdqs function is available in x8 ddr3l sdram only
1gb ddr3l C as4c128m8d3l confidential 18 rev. 2 . 0 a ug . / 20 1 4 ? mode register mr2 the mode register mr2 stores the data for controlling refresh related features, rtt_wr impedance, and c as write latency. the mode register 2 is written by asserting low on cs# , ras# , cas# , we#, high on ba1 and low on ba0 and ba2, while controlling the states of address pins according to the table below. table 8 . extended mode register emr ( 2 ) bitmap b a2 ba 1 b a0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 1 0 0 *1 rtt_wr 0 *1 srt asr cwl pasr mode register (2) ba1 ba0 mrs mode a6 auto self - refresh (asr) 0 0 mr0 0 manual sr reference (srt) 0 1 mr 1 1 asr enable (optional) 1 0 mr2 1 1 mr3 a10 a9 rtt_wr *2 a2 a1 a0 partial array self - refresh (optional) 0 0 dynamic odt off (write does not affect rtt value) 0 1 rzq/4 0 0 0 full array 1 0 rzq/2 0 0 1 halfarray (ba[2:0]=000,001,010,&011) 1 1 reserved 0 1 0 quarter array (ba[2:0]=000,&001) 0 1 1 1/8 th array (ba[2:0]=000) 1 0 0 3/4 array (ba[2:0]=010,011,100.101,110,&111) 1 0 1 halfarray (ba[2:0]=100,101,110,&111) 1 1 0 q uarter array (ba[2:0]=110,&111) 1 1 1 1/8 th array (ba[2:0]=111) a7 self - refresh temperature (srt) range a5 a4 a3 cas write latency (cwl) 0 normal operating temperature range 0 0 0 5 (tck(avg) R 2.5ns) 1 extended (optional ) operating temperature range 0 0 1 6 (2.5ns tck(avg) R 1.875ns) 0 1 0 7 (1.875ns tck(avg) R 1.5ns) 0 1 1 8 (1.5ns tck(avg) R 1.25ns) 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved note 1 : ba2 and a8, a 11~ a1 3 are r fu and must be programmed to 0 during mrs . note 2: the rtt_wr value can be applied during writes even when rtt_nom is disabled. during write leveling, dynamic odt is not available.
1gb ddr3l C as4c128m8d3l confidential 19 rev. 2 . 0 a ug . / 20 1 4 - partial array self - refresh (pasr) optional in ddr3l sdra m: users should refer to the dram supplier data sheet and/or the dimm spd to determine if ddr3l sdram devices support the following options or requirements referred to in this material. if pasr (partial array self - refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self - refresh is entered. data integrity will be maintained if trefi conditions are met and no self - refresh command is issued. - cas write latency (cwl) the cas write latency is defined by mr 2 (bits a3 - a5) shown in mr2. cas write latency is the delay, in clock cycles, between the internal write command and the availability of the first bit of input data. ddr3l dram does not support any half clock latencies. the overall write latency (wl) is de fined as additive latency (al) + cas write latency (cwl); wl=al+cwl. for more information on the supported cwl and al settings based on the operating clock frequency, refer to standard speed bins. for detailed write operation refer to write operation. - auto self - refresh (asr) and self - refresh temperature (srt) ddr3l sdram must support self - refresh operation at all supported temperatures. applications requiring self - refresh operation in the extended temperature range must use the asr function or progra m the srt bit appropriately. optional in ddr3l sdram: users should refer to the dram supplier data sheet and/or the dimm spd to determine if ddr3l sdram devices support the following options or requirements referred to in this material. for more details r efer to extended temperature usage. ddr3l sdrams must support self - refresh operation at all supported temperatures. applications requiring self - refresh operation in the extended temperature range must use the optional asr function or program the srt bit appropriately. - dynamic odt (rtt_wr) ddr3l sdram introduces a new feature dynamic odt. in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3l sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt settings. ddr3l sdram introduces a new feature dynamic odt. in certain application cases and to further enhance signal integrity on the data bus, it is desirabl e that the termination strength of the ddr3l sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt settings. in write leveling mode, only rtt_nom is available. for details on dynamic odt operation, refer to dynamic odt.
1gb ddr3l C as4c128m8d3l confidential 20 rev. 2 . 0 a ug . / 20 1 4 ? mode register mr3 the mode register mr3 controls multi - purpose registers. the mode register 3 is written by asserting low on cs# , ras# , cas# , we# , high on ba1 and ba0, and low on ba2 while controlling the states of address pins a ccording to the table below table 9 . extended mode register emr ( 3 ) bitmap b a2 ba1 b a0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 1 1 0 *1 mpr mpr loc mode register (3) ba1 ba0 mrs mode a2 mpr a1 a0 mpr location 0 0 mr0 0 normal operation *3 0 0 predefined pattern *2 0 1 mr1 1 dataflow from mpr 0 1 rfu 1 0 mr2 1 0 rfu 1 1 mr3 1 1 rfu note 1 : ba2, a3 - a1 3 are rfu and must be programmed to 0 during mrs. note 2: the predefined patt ern will be used for read synchronization. note 3: when mpr control is set for normal operation (mr3 a [2] = 0) then mr3 a[1:0] will be ignored.
1gb ddr3l C as4c128m8d3l confidential 21 rev. 2 . 0 a ug . / 20 1 4 table 10 . absolute maximum dc rating s symbol parameter rating unit note v dd voltage on vdd pin relative t o vss - 0.4 ~ 1. 8 v 1,3 v ddq voltage on vddq pin relative to vss - 0. 4 ~ 1. 8 v 1,3 v in , v out voltage on any pin relative to vss - 0. 4 ~ 1. 8 v 1 t stg storage t emperature - 55~1 0 0 c 1 ,2 n ote1 : stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied . exposure to absolute maximum rating conditions for extended periods may affect reliability. note2: storage temperature is the case surface temperature on the center/top side of the dram. note3: vdd and vddq must be within 300mv of each other at all times ; and vref must be not greater than 0.6vddq, when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. table 1 1 . temperature range symbol parameter rating unit note t oper operating case t emperature range 0~ 8 5 c 1,2 extended temperature range 85 ~ 9 5 c 1, 3 industrial temperature range - 40 ~ 9 5 c 1 - 4 n ote 1: operating temperature is the case surface temperature on center/top of the dram. note2: the operating temperat u r e range is the temperature where all dram specification will be supported. outside of this temperature range, even if it is still within the limit of stress condition, some deviation on portion of operating specification may be required. during operatio n, the dram case temperature must be maintained between 0 - 85 c under all other specification parameter. supporting 0 - 85 c with full jedec ac & dc specifications. note3: some applications require operation of the dram in the extend ed temperature range between 85 c and 95 c case temperature. full specifications are guaranteed in this range, but the following additional apply. a) refresh commands must be doubled in frequency, therefore, reducing the refresh interval trefi to 3.9us. it is also possible to specify a component with 1x refresh (trefi to 7.8us) in the extended temperature range. b) if self - refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self - refresh mode with extended temperature range capability (mr2 a6=0 and mr2 a7=1) or enable the optional auto self - refresh mode (mr2 a6=1 and mr2 a7=0). note4: during industrial temperature operation range, the dram case temperature must be maintained between - 40c~95c under all operating conditions. table 12 . recommended dc operating conditions symbol parameter operation voltage rating units note min. typ. max v dd supply voltage 1.35v 1.283 1.35 1.45 v 1,2,3 1.5v 1.425 1.5 1.575 v 1,2,3 v ddq supply volt age for output 1.35v 1.283 1.35 1.45 v 1,2,3 1.5v 1.425 1.5 1.575 v 1,2,3 notes: 1. under all conditions v ddq must be less than or equal to v dd 2. v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together. 3. v dd & v ddq rating are determi ned by operation voltage.
1gb ddr3l C as4c128m8d3l confidential 22 rev. 2 . 0 a ug . / 20 1 4 table 13. single - ended ac and dc input levels for command and address symbol parameter - 12 unit n ote min. max. v ih .ca(dc 90 ) dc input logic high v ref + 0. 09 v dd v 1,5 v il .ca(dc 90 ) dc input logic lo w v ss v ref - 0. 09 v 1,6 v ih .ca(ac1 60 ) ac input logic high v ref + 0.1 6 - v 1,2,7 v il .ca(ac1 60 ) ac input logic low - v ref C 0.1 6 v 1,2,8 v ih .ca(ac1 35 ) ac input logic high v ref + 0.1 3 5 - v 1,2,7 v il .ca(ac1 35 ) ac input logic low - v ref C 0.1 3 5 v 1,2,8 v refca (dc) r eference voltage for add, cmd inputs 0.49 x v dd 0.51 x v dd v 3,4 note 1 : for input only pins except reset#. vref = vrefca(dc). note 2 : see overshoot and undershoot specifications . note 3 : the ac peak noise on vref may not allow vref to deviate from vrefca(dc) by more than +/ - 1% vdd . note 4 : for reference: approx. vdd/2 +/ - 1 3. 5 mv. note 5 : vih(dc) is used as a simplified symbol for vih.ca(dc 9 0) note 6 : vil(dc) is used as a simplified symbol for vil.ca(dc 9 0) note 7 : vih(ac) is used as a simplified symbol for vih.ca(ac1 60 ), vih.ca(ac1 35 ) and vih.ca(ac1 60 ) value is used when vref + 0.1 6 v is referenced, vih.ca(ac1 35 ) value is used when vref + 0.1 35 v is referenced . note 8 : vil(ac) is used as a simplified symbol for vil.ca(ac1 60 ), vil.ca(ac1 35 ) and vil.ca(ac1 60 ) value is used when vref - 0.1 6 v is referenced, vil.ca(ac1 35 ) value is used when vref - 0.1 35 v is referenced . table 1 4 . single - ended ac a nd dc input levels for dq and dm symbol parameter - 12 unit note min. max. v ih . dq (dc 9 0) dc input logic high v ref + 0. 09 v dd v 1,5 v il . dq (dc 9 0) dc input logic lo w v ss v ref C 0. 09 v 1,6 v ih . dq (ac1 35 ) ac input logic high v ref + 0.1 3 5 - v 1,2,7 v il . dq ( ac1 35 ) ac input logic low - v ref C 0.1 3 5 v 1,2,8 v ref dq (dc) r eference voltage for dq , dm inputs 0.49 x v dd 0.51 x v dd v 3,4 note 1 : vref = vrefdq(dc). note 2 : see overshoot and undershoot specifications. note 3 : the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd . note 4 : for reference: approx. vdd/2 +/ - 1 3. 5 mv. note 5 : vih(dc) is used as a simplified symbol for vih.dq(dc 9 0) note 6 : vil(dc) is used as a simplified symbol for vil.dq(dc 9 0) note 7 : vih(ac) is use d as a simplified symbol for vih.dq(ac1 35 ) and vih.dq(ac1 3 5) value is used when vref + 0.1 3 5v is referenced . note 8 : vil(ac) is used as a simplified symbol for vil.dq(ac1 35 ) and vil.dq(ac1 35 ) value is used when vref - 0.1 3 5v is referenced .
1gb ddr3l C as4c128m8d3l confidential 23 rev. 2 . 0 a ug . / 20 1 4 table 15. dif ferential ac and dc input levels symbol parameter - 12 unit note min. max. v ih diff differential input high 0. 18 - v 1 , 3 v il diff differential input logic low - - 0.18 v 1, 3 v ih diff( ac ) differential input high ac 2 x (v ih ( ac ) - v ref ) - v 2 , 3 v il di ff( ac ) differential input low ac - 2 x (v i l ( ac ) - v ref ) v 2 , 3 note 1 : used to define a differential signal slew - rate. note 2 : for ck - ck# use vih/vil(ac) of add/cmd and vrefca; for dqs, dqs# use vih/vil(ac) of dqs and vrefdq; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here. note 3 : these values are not defined; however, the single - ended signals ck, ck#, dqs, dqs# need to be within the respective limits (vih(dc) max, vil(dc)min) for single - ended si gnals as well as the limitations for overshoot and undershoot. table 16 . capacitance (v dd = 1. 3 5 v, f = 1mhz, t oper = 25 ? c i o input/output capacitance , (dq, dm, dqs, dqs# , t dqs, t dqs#) 1.5 2.3 pf 1, 2, 3 c ck input capacitance, ck and ck# 0.8 1.4 pf 2, 3 c dck input capacitance delta, ck and ck# 0 0.15 pf 2, 3, 4 c ddqs input/output capacitance delta , dqs and dqs# 0 0.15 pf 2, 3, 5 c i input capacitance , (ctrl, add, cmd input - only pins) 0.75 1.3 pf 2, 3, 6 c di_ctrl input capacitance delta, (all ctrl input - only pins ) - 0.4 0.2 pf 2, 3, 7, 8 c di_add_cmd input capacitance delta, (all add , cmd input - only pins) - 0.4 0.4 pf 2, 3, 9, 10 c dio input/output capacitance delta, (dq, dm, dqs, dqs# , t dqs, t d qs#) - 0.5 0.3 pf 2, 3, 11 c zq input/output capacitance of zq pin - 3 pf 2, 3, 12 note 1 : although the dm , tdqs and tdqs# pins have different functions, the loading matches dq and dqs . note 2 : this parameter is not subject to production test. it is verifi ed by design and characterization. vdd=vddq=1. 3 5v, vbias=vdd/2 and on die termination off. note 3 : this parameter applies to monolithic devices only; stacked/dual - die devices are not covered here . note 4 : absolute value of cck - cck# . note 5 : absolute value of cio(dqs) - cio(dqs#) . note 6 : ci applies to odt, cs#, cke, a0 - a1 3 , ba0 - ba2, ras#, cas#, we#. note 7 : cdi_ctrl applies to odt, cs# and cke . note 8 : cdi_ ctrl=ci(ctrl) - 0.5*(ci(ck)+ci(c k#)) . note 9 : cdi_add_cmd applies to a0 - a1 2 , ba0 - ba2, ras#, cas# and we# . note 10 : cdi_ add_cmd=ci(add_cmd) - 0.5*(ci(ck)+ci(c k#)) . note 11 : cdio=cio(dq,dm) - 0.5*(cio(dqs)+cio(dqs#)) . note 12 : maximum external load capacitance on zq pin: 5 pf.
1gb ddr3l C as4c128m8d3l confidential 24 rev. 2 . 0 a ug . / 20 1 4 table 17 . idd specification parameters and test conditions (v dd = 1. 3 5 v) parameter & test condition symbol - 12 unit max. operating one bank active - precharge current cke: high; external clock: on; bl: 8 *1 ; al: 0; cs# : high between act and pre; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd0 40 ma operating one bank active - read - precharge current cke: high; external clock: on; bl: 8 *1, 7 ; al: 0; cs# : high between act, rd and pre; command, address, bank address inputs, data io: partially toggling; dm :stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...; output buffer and rtt: enabled in mode registers *2 ; odt sig nal: stable at 0 . i dd1 4 5 ma precharge standby current cke : high; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd2n 2 0 ma precharge power - down current slow exit cke: low; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level ; dm :stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0; p r echarge power down mode : slow exit . *3 i dd2p0 10 ma precharge power - down current fast exit cke: low; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm :stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0; p r echarge power down mode : fa st exit . *3 i dd2p1 1 2 ma precharge quiet standby current cke : high; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm :stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd2q 1 6 ma active standby current cke : high; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd3n 25 ma active power - down current cke: low; external clock: on; bl: 8 *1 ; al: 0; cs# : stable at 1; command, address, bank address inputs: stab le at 0; data io: mid - level; dm :stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 i dd3p 1 7 ma operating burst read current cke: high; external clock: on; bl: 8 *1, 7 ; al: 0; cs# : high bet ween rd; command, address, bank address inputs: partially toggling; dm :stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,... ; tput buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd4r 90 ma o perating burst write current cke: high; external clock: on; bl: 8 *1 ; al: 0; cs# : high between wr; command, address, bank address inputs: partially toggling; dm: stable at 0; bank activity: all banks open . output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at high . i dd4w 95 ma
1gb ddr3l C as4c128m8d3l confidential 25 rev. 2 . 0 a ug . / 20 1 4 burst refresh current cke: high; external clock: on; bl: 8 *1 ; al: 0; cs# : high between t ref; command, address, bank address inputs: partially toggling; data io: mid - level; dm :stable at 0; bank activity: ref comma nd every t rfc; output buffer and rtt: enabled in mode registers *2 ; odt signal: stable at 0 . i dd5b 9 0 ma self refresh current: auto self - refresh (asr) : disabled *4 ; self - refresh temperature range (srt): normal *5 ; cke: low; external clock: off; ck and ck#: low; bl: 8 *1 ; al: 0; cs#, command, address, bank address, data io: mid - level; dm :stable at 0; bank activity: self - refresh operation; output buffer and rtt: enabled in mode registers *2 ; odt signal: mid - level t case : 0 - 85c i dd6 1 0 ma t case : - 4 0 - 9 5c i dd 6et 11 ma operating bank interleave read current cke: high; external clock: on; bl: 8 *1, 7 ; al: cl - 1; cs# : high between act and rda; command, address, bank address inputs: partially toggling; dm :stable at 0; output buffer and rtt: enabled in mode register s *2 ; odt signal: stable at 0 . i dd7 130 ma reset low current reset: low; external clock: off; ck and ck#: low; cke: floating; cs# , command, address, bank address, data io: floating; odt signal: floating reset low current reading is valid once power is stab le and reset has been low for at least 1ms. i dd 8 10 ma note 1 : burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b note 2 : output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10, 9] = 10b note 3 : pecharge power down mode: set mr0 a12=0b for slow exit or mr0 a12=1b for fast exit note 4 : auto self - refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature note 5 : self - refresh temperature range (srt): set mr2 a7=0b for normal o r 1b for extended temperature range note 6 : refer to dram supplier data sheet and/or dimm spd to determine if optional features or requirements are supported by ddr3l sdram device note 7 : read burst type: nibble sequential, set mr0 a[3] = 0b
1gb ddr3l C as4c128m8d3l confidential 26 rev. 2 . 0 a ug . / 20 1 4 table 18 . electrical characteristics and recommended a.c. operating conditions (v dd = 1 . 3 5 v) symbol parameter - 12 unit note min. max. t aa internal read command to first data 13.75 20 ns t rcd act to internal read or write delay time 13.75 - ns t rp pre command period 13.75 - ns t rc act to act or ref command period 48 .75 - ns t ras active to precharge command period 3 5 9 * t refi ns t ck(avg) average clock period cl=5, cwl=5 3.0 <3.3 ns cl=6, cwl=5 2.5 <3.3 ns cl=7, cwl=6 1.875 <2.5 ns 33 cl=8, cwl= 6 1.875 <2.5 ns 33 cl=9, cwl=7 1.5 <1.875 ns 33 cl=10, cwl= 7 1.5 <1.875 ns 33 cl=1 1 , cwl=8 1.25 <1. 5 ns 33 t ck (dll_off) minimum clock cycle time (dll off mode) 8 - ns 6 t ch(avg) average clock high pulse width 0.47 0.53 t ck t cl(avg) average clock low pulse width 0.47 0.53 t ck t dqsq dqs, dqs# to dq skew, per group, per access - 100 ps 13 t qh dq output hold time from dqs, dqs# 0.38 - t ck 13 t lz(dq) dq low - impedance time from ck, ck# - 450 225 ps 13,14 t hz(dq) dq high impedance time from ck, ck# - 225 ps 13,14 t ds(base) da ta setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels ac1 35 25 - ps 17 t dh(base) data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels dc 90 55 - ps 17 t dipw dq and dm input pulse width for each input 360 - ps t rpre dqs,dqs# differential read preamble 0.9 - t ck 13,19 t rpst dqs, dqs# differential read postamble 0.3 - t ck 11,13 t qsh dqs, dqs# differential output high time 0.4 - t ck 13 t qsl dqs, dqs# differential output low time 0.4 - t ck 13 t wpre dqs, dqs# differential writ e preamble 0.9 - t ck 1 t wpst dqs, dqs# differential write postamble 0.3 - t ck 1 t dqsck dqs, dqs# rising edge output access time from rising ck, ck# - 225 225 ps 13 t lz(dqs) dqs and dqs# low - impedance time (referenced from rl - 1) - 450 225 ps 13, 14 t hz( dqs) dqs and dqs# high - impedance time (referenced from rl + bl/2) - 225 ps 13, 14 t dqsl dqs, dqs# differential input low pulse width 0.45 0.55 t ck 29, 31 t dqsh dqs, dqs# differential input high pulse width 0.45 0.55 t ck 30, 31 t dqss dqs, dqs# rising edg e to ck, ck# rising edge - 0.27 0.27 t ck t dss dqs, dqs# falling edge setup time to ck, ck# rising edge 0.18 - t ck 32 t dsh dqs, dqs# falling edge hold time from ck, ck# rising edge 0.18 - t ck 32 t dllk dll locking time 512 - t ck
1gb ddr3l C as4c128m8d3l confidential 27 rev. 2 . 0 a ug . / 20 1 4 t rtp internal read comma nd to precharge command delay max (4 t ck , 7.5ns) - t ck t wtr delay from start of internal write transaction to internal read command max (4 t ck , 7.5ns) - t ck 1 8 t wr write recovery time 15 - ns 18 t mrd mode register set command cycle time 4 - t ck t mod mo de register set command update delay ma x 12 t ck , 15ns) - t ck t ccd cas# to cas# command delay 4 - t ck t dal(min) auto precharge write recovery + prechargetime wr + t rp t ck t mprr multi - purpose register recovery time 1 - t ck 22 t rrd active to active comm and period max (4 t ck , 6 ns) - t ck t faw four activate window 30 - ns t is(base) command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels ac1 60 60 - ps 16 ac1 35 185 - ps 16,27 t ih(base) command and address hold time from ck, ck # referenced to vih(dc) / vil(dc) levels dc 90 1 30 - ps 16 t ipw control and address input pulse width for each input 560 - ps 28 t zqinit power - up and reset calibration time 512 - t ck t zqoper normal operation full calibration time 256 - t ck t zqcs norma l operation short calibration time 64 - t ck 23 t xpr exit reset from cke high to a valid command max(5 t ck , t rfc(min) + 10ns) - t ck t xs exit self refresh to commands not requiring a locked dll max(5 t ck , t rfc(min) + 10ns) - t ck t xsdll exit self refresh t o commands requiring a locked dll tdllk (min) - t ck t ckesr minimum cke low width for self refresh entry to exit timing tcke (min) + 1 t ck - t ck t cksre valid clock requirement after self refresh entry (sre) or power - down entry (pde) max(5 t ck , 10 ns) - t ck t cksrx valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit max(5 t ck , 10 ns) - t ck t xp exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a lock ed dll max( 3t ck , 6 ns) - t ck t xpdll exit precharge power down with dll frozen to commands requiring a lockeddll m ax ( 10t ck , 24 ns) - t ck 2 t cke cke minimum pulse width max( 3t ck , 5 ns) - t ck t cpded command pass disable delay 2 - t ck t pd power down entry to exit timing tcke (min) 9 * t refi 15 t actpden timing of act command to power down entry 1 - t ck 20 t prpden timing of pre or prea command to power down entry 1 - t ck 20
1gb ddr3l C as4c128m8d3l confidential 28 rev. 2 . 0 a ug . / 20 1 4 t rdpden timing of rd/rda command to power down entry rl + 4 + 1 - t ck t wrp den timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) wl + 4 + (t wr / t ck ) - t ck 9 t wrapden timing of wra command to power down entry (bl8otf, bl8mrs,bc4otf) wl + 4 + wr + 1 - t ck 10 t wrpden timing of wr command to power down entry (bc4m rs) wl + 2 + (t wr / t ck ) - t ck 9 t wrapden timing of wra command to power down entry (bc4mrs) wl + 2 + wr + 1 - t ck 10 t refpden timing of ref command to power down entry 1 - t ck 20, 21 t mrspden timing of mrs command to power down entry tmod (min) - od tlon odt turn on latency wl - 2 = cwl + al - 2 t ck odtloff odt turn off latency wl - 2 = cwl + al - 2 odth4 odt high time without write command or with write command and bc4 4 - t ck odth8 odt high time with write command and bl8 6 - t ck t aonpd as ynchronous rtt turn - on delay (power - down with dll frozen) 2 8.5 ns t aofpd asynchronous rtt turn - off delay (power - down with dll frozen) 2 8.5 ns t aon rtt turn - on - 225 225 ps 7 t aof rtt_nom and rtt_wr turn - off time from odtloff reference 0.3 0.7 t ck 8 t adc rtt dynamic change skew 0.3 0.7 t ck t wlmrd first dqs/dqs# rising edge after write leveling mode is programmed 40 - t ck 3 t wldqsen dqs/dqs# delay after write leveling mode is programmed 25 - t ck 3 t wls write leveling setup time from rising ck, ck # crossing to rising dqs, dqs# crossing 165 - ps t wlh write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing 165 - ps t wlo write leveling output delay 0 7.5 ns t wloe write leveling output error 0 2 ns t rfc ref command to act or ref command time 110 - ns t refi average periodic refresh interval - 4 0c to 85c - 7.8 s 85 c to 9 5c - 3.9 s note 1: actual value dependant upon measurement level. note 2: commands requiring a locked dll are: read (and rap) and synchronous odt commands. note 3: the max values are system dependent. note 4: wr as programmed in mode r egister . note 5: value must be rounded - up to next higher integer value note 6: there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. note 7 : for definition of rtt turn - on time taon see timing parameters . note 8 : fo r definition of rtt turn - off time taof see timing parameters . note 9 : twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. note 10 : wr in clock cycles as programmed in mr0. note 11 : the maximum read postamble is bound by tdqsck(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. see clock to data strobe relationship .
1gb ddr3l C as4c128m8d3l confidential 29 rev. 2 . 0 a ug . / 20 1 4 note 12 : output timing deratings are relative to the sdram input clock. when the device is operated with input clo ck jitter, this parameter needs to be derated by t.b.d. note 13 : value is only valid for ron34 . note 14 : single ended signal parameter. note 15 : trefi depends on toper .
1gb ddr3l C as4c128m8d3l confidential 30 rev. 2 . 0 a ug . / 20 1 4 note 16 : tis(base) and tih(base) values are for 1v/ns cmd/add single - ended slew rate and 2v/ns ck, ck# differential slew rate. note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except reset#, vref(dc) = vrefca(dc). see address / command setup, hold and derating . note 17 : tds(base) and tdh(base) values are for 1v/ns d q single - ended slew rate and 2v/ns dqs, dqs# differential slew rate. note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except reset#, vref(dc) = vrefca(dc). see data setup, hold and slew rate derating . note 18 : start of internal writ e transaction is defined as follows: - for bl8 (fixed by mrs and on - the - fly): rising clock edge 4 clock cycles after wl. - for bc4 (on - the - fly): rising clock edge 4 clock cycles after wl. - for bc4 (fixed by mrs): rising clock edge 2 clock cycles aft er wl. note 19 : the maximum read preamble is bound by tlz(dqs)min on the left side and tdqsck(max) on the right side. see clock to data strobe relationship . note 20 : cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power - down idd spec will not be applied until finishing those operations. note 21 : although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where add itional time such as txpdll(min) is also required. see power - down clarifications - case 2 . note 22 : defined between end of mpr read burst and mrs which reloads mpr or disables mpr function. note 23 : one zqcs command can effectively correct a minimum of 0.5 % (zq correction) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the output driver voltage and temperature sensitivity and odt voltage and temperature sensitivity tables. the appropriate interval between zqcs commands can be determined from these tables and other application - specific parameters. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the s dram is subject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max(drttdt, dr ondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5% / oc, vsens = 0.15% / mv, tdriftrate = 1 oc / sec and vdriftrate = 15 mv / sec, then the interval between zqcs comma nds is calculated as: note 24 : n = from 13 cycles to 50 cycles. this row defines 38 parameters. note 25 : tch(abs) is the absolute instantaneous clock high pulse widt h, as measured from one rising edge to the following falling edge. note 26 : tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. note 27 : the tis(base) ac1 35 specifications are adjust ed from the tis(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 1 35 mv and another 25 ps to account for the earlier reference point [(1 60 mv - 1 3 5 mv) / 1 v/ns]. note 28 : pulse width of a i nput signal is defined as the width between the first crossing of vref(dc) and the consecutive crossing of vref(dc). note 29 : tdqsl describes the instantaneous differential input low pulse width on dqs - dqs#, as measured from one falling edge to the next consecutive rising edge. note 30 : tdqsh describes the instantaneous differential input high pulse width on dqs - dqs#, as measured from one rising edge to the next consecutive falling edge. note 31 : tdqsh,act + tdqsl,act = 1 tck,act ; with txyz,act being t he actual measured value of the respective timing parameter in the application. note 32 : tdsh,act + tdss,act = 1 tck,act ; with txyz,act being the actual measured value of the respective timing parameter in the application. note 33: the cl and cwl settings result in tck requirements. when making a selection of tck, both cl and cwl requirement settings need to be fulfilled. ( t s e n s t d r i f t r a t e ) + ( v s e n s v d r i f t r a t e ) z q c o r r e c t i o n ( 1 . 5 1 ) + ( 0 . 1 5 1 5 ) 0 . 5 = 0 . 1 3 3 1 2 8 m s
1gb ddr3l C as4c128m8d3l confidential 31 rev. 2 . 0 a ug . / 20 1 4 - multi - purpose register (mpr) the multi purpose register (mpr) function is used to read out a predefined system timing calibrat ion bit sequence. figure 8 . mpr block diagram to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2 = 1 . prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. the resulting operation, when a rd or rda command is issued, is defined by mr3 bits a[1:0] when the mpr is enabled a s shown in table 11 . when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2 = 0). note that in mpr mode rda has the same functionality as a read command which means the auto p recharge part of rda is ignored. power - down mode, self - refresh and any other non - rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. table 1 9 . mpr mr 3 register definition mr3 a[2] mr3 a[1:0] funct ion mpr mpr - loc 0b d on t care (0b or 1b) normal operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent write will go to dram array. 1b see the table11 enable mpr mode, subsequent rd/rda commands defined by mr3 a[1 :0]. m e m o r y c o r e ( a l l b a n k s p r e c h a r g e d ) m r s 3 a 2 d q , d m , d q s , d q s # m u l t i p u r p o s e r e g i s t e r p r e - d e f i n e d d a t a f o r r e a d s
1gb ddr3l C as4c128m8d3l confidential 32 rev. 2 . 0 a ug . / 20 1 4 - mpr functional description ?one bit wide logical interface via all dq pins during read operation. ?register read on x 8 : ?dql[0] drive information from mpr. ?dql[7:1] either drive the same information as dql [0], or they drive 0b. ?addres sing during for multi purpose register reads for all mpr agents: ?ba [2:0]: dont care ?a[1:0]: a[1:0] must be equal to 00b. data read burst order in nibble is fixed ?a[2]: for bl=8, a[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) for burst chop 4 cases, the burst order is switched on nibble base a [2]=0b, burst order: 0,1,2,3 *) a[2]=1b, burst order: 4,5,6,7 *) ?a[9:3]: dont care ?a10/ap: dont care ?a12/bc: selects burst chop mode on - the - fly, if enabled within mr0. ?a11 , a13, .. . (if available): dont care ?regular interface functionality during register reads: ?support two burst ordering which are switched with a2 and a[1:0]=00b. ?support of read burst chop (mrs and on - the - fly via a12/bc) ?all other address bits (remaining colum n address bits including a10, all bank address bits) will be ignored by the ddr3l sdram. ?regular read latencies and ac timings apply. ?dll must be locked prior to mpr reads. note: *) burst order bit 0 is assigned to lsb and burst order bit 7 is assigned t o msb of the selected mpr agent. table 20 . mpr mr3 register definition mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst order and data pattern 1b 00b read predefined pattern for system calibration bl8 000b burst order 0, 1, 2, 3, 4 , 5, 6, 7 pre - defined data pattern [0, 1, 0, 1, 0, 1, 0, 1] bc4 000b burst order 0, 1, 2, 3 pre - defined data pattern [0, 1, 0, 1] bc4 100b burst order 4, 5, 6, 7 pre - defined data pattern [0, 1, 0, 1] 1b 01b rfu bl8 000b burst order 0, 1, 2, 3, 4, 5, 6, 7 bc4 000b burst order 0, 1, 2, 3 bc4 100b burst order 4, 5, 6, 7 1b 10b rfu bl8 000b burst order 0, 1, 2, 3, 4, 5, 6, 7 bc4 000b burst order 0, 1, 2, 3 bc4 100b burst order 4, 5, 6, 7 1b 11b rfu bl8 000b burst order 0, 1, 2, 3, 4, 5, 6, 7 bc4 000b burst order 0, 1, 2, 3 bc4 100b burst order 4, 5, 6, 7 ? no operation (nop) command the no operation (nop) command is used to i nstruct the selected ddr3l sdram to perform a nop ( cs# low and ras# , cas# and we# high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. ? deselect command the deselect function ( cs# high) prevents new commands from being executed by the ddr3l sdram. the ddr3l sdram is effecti vely deselected. operations already in progress are not affected.
1gb ddr3l C as4c128m8d3l confidential 33 rev. 2 . 0 a ug . / 20 1 4 ? dll - off mode ddr3l dll - off mode is entered by setting mr1 bit a0 to 1 ; this will disable the dll for subsequent operations until a0 bit set back to 0. the mr1 a0 bit for dll control can be switched either during initialization or later. the dll - off mode operations listed below ar e an optional feature for ddr3l . the maximum clock frequency for dll - off mode is specified by the parameter tckdll_off. there is no minimum frequency limit be sides the need to satisfy the refresh interval, trefi. due to latency counter and timing restrictions, only one value of cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll - off mode is only required to support setting of both cl=6 and cwl=6. dll - off mode will affect the read data clock to data strobe relationship (tdqsck) but not the data strobe to data relationship (tdqsq, tqh). special attention is needed to line up read data to controller time domain. comparing with dll - on mode, where tdqsck starts from the rising clock edge (al+cl) cycles after the read command, the dll - off mode tdqsck starts (al+cl - 1) cycles after the read command. another difference is that tdqsck may not be small compared to tck (it might even be larger than tck) and the difference between tdqsckmin and tdqsckmax is significantly larger than in dll - on mode. the timing relations on dll - off mode read operation have shown at the following timing diagram (cl=6, bl=8) figure 9 . dll - off mode read timing opera tion c k # t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 0 a d d r e s s c k t 1 0 c o m m a n d d q s # d q s d o n ' t c a r e n o p r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p b a n k , c o l b r l ( d l l _ o n ) = a l + c l = 6 ( c l = 6 , a l = 0 ) c l = 6 d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 d q d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 d q s # d q s d q d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 d q s # d q s d q ( d l l _ o n ) ( d l l _ o n ) ( d l l _ o f f ) ( d l l _ o f f ) ( d l l _ o f f ) ( d l l _ o f f ) r l ( d l l _ o f f ) = a l + ( c l - 1 ) = 5 t d q s c k ( d l l _ o f f ) _ m i n t d q s c k ( d l l _ o f f ) _ m a x n o t e 1 . t h e t d q s c k i s u s e d h e r e f o r d q s , d q s # a n d d q t o h a v e a s i m p l i f i e d d i a g r a m ; t h e d l l _ o f f s h i f t w i l l a f f e c t b o t h t i m i n g s i n t h e s a m e w a y a n d t h e s k e w b e t w e e n a l l d q a n d d q s , d q s # s i g n a l s w i l l s t i l l b e t d q s q . t r a n s i t i o n i n g d a t a
1gb ddr3l C as4c128m8d3l confidential 34 rev. 2 . 0 a ug . / 20 1 4 ? dll on/off switching procedure ddr3l dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operation until a0 bit set back to 0. ? dll on to dll off procedure to swi tch from dll on to dll off requires the frequency to be changed during self - refresh outlined in the following procedure: 1 . starting from idle state (all banks pre - charged, all timing fulfilled, and drams on - die termination resistors, rtt, must be in h igh impedance state before mrs to mr1 to disable the dll). 2 . set mr1 bit a0 to 1 to disable the dll. 3 . wait tmod. 4. enter self refresh mode; wait until (tcksre) satisfied. 5 . change frequency, in guidance with input clock frequency change section. 6 . wait until a stable clock is available for at least (tcksrx) at dram inputs. 7. starting with the self refresh exit command, cke must continuously be registered high until all tmod timings from any mrs command are satisfied. in addition, if any odt featu res were enabled in the mode registers when self refresh mode was entered, the odt signal must continuously be registered low until all tmod timings from any mrs command are satisfied. if both odt features were disabled in the mode registers when self refr esh mode was entered, odt signal can be registered low or high. 8. wait txs, and then set mode registers with appropriate values (especially an update of cl, cwl, and wr may be necessary. a zqcl command may also be issued after txs). 9. wait for tmod, and then dram is ready for next command. figure 10 . dll switch sequence from dll - on to dll - off t 1 t a 0 t a 1 t b 0 t c 0 t d 0 t d 1 t e 0 t e 1 t 0 t f 0 t m o d n o t e s 1 d o n ' t c a r e t i m e b r e a k n o p m r s s r e n o p s r x n o p m r s n o p v a l i d v a l i d t c k s r e n o t e s 2 n o t e s 3 n o t e s 6 n o t e s 7 n o t e s 8 n o t e s 8 n o t e s 4 t c k s r x n o t e s 5 t x s t m o d t c k e s r v a l i d n o t e s 8 n o t e s : 1 . s t a r t i n g w i t h i d l e s t a t e , r t t i n h i - z s t a t e 2 . d i s a b l e d l l b y s e t t i n g m r 1 b i t a 0 t o 1 3 . e n t e r s r 4 . c h a n g e f r e q u e n c y 5 . c l o c k m u s t b e s t a b l e t c k s r x 6 . e x i t s r 7 . u p d a t e m o d e r e g i s t e r s w i t h d l l o f f p a r a m e t e r s s e t t i n g 8 . a n y v a l i d c o m m a n d o d t : s t a t i c l o w i n c a s e r t t _ n o m a n d r t t _ w r i s e n a b l e d , o t h e r w i s e s t a t i c l o w o r h i g h c k # c k c o m m a n d c k e o d t
1gb ddr3l C as4c128m8d3l confidential 35 rev. 2 . 0 a ug . / 20 1 4 ? dll off to dll on procedure to switch from dll off to dll on (with requires frequency change) during self - refresh: 1 . starting from idle state (all banks pre - charged, all timings fulfilled and dra ms on - die termination resistors (rtt) must be in high impedance state before self - refresh mode is entered). 2 . enter self refresh mode, wait until tcksre satisfied. 3. change f requency, in guidance with input clock frequency change section. 4. wait until a stable clock is available for at least (tcksrx) at dram inputs. 5 . starting with the self refresh exit command, cke must continuously be registered high until tdllk timing f rom subsequent dll reset command is satisfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered , the odt signal must continuously be registered low until tdllk timings from subsequent dll reset command is satisfied. if both odt features are disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 6 . wait txs, then set mr1 bit a0 to 0 to enable the dll. 7 . wait tmrd, then set mr0 bit a8 to 1 to start dll reset. 8 . wait tmrd, then set mode registers with appropriate values (especially an update of cl, cwl, and wr may be necessary. after tmod satisfied from any proceeding mrs command, a zqcl command may also be issued during or after tdllk). 9. wait for tmod, then dram is ready for next command (remember to wait tdllk after dll reset before applying command requiring a locked dll!). in addition, wait also for tzqoper in case a zqcl command was issued. figure 11 . dll switch sequence from dll - off to dll on c k # t a 0 t a 1 t b 0 t c 0 t c 1 t d 0 t e 0 t f 1 t g 0 t 0 c k t h 0 c o m m a n d c k e o d t n o t e s 1 d o n ' t c a r e t i m e b r e a k s r e n o p n o p s r x m r s m r s m r s v a l i d v a l i d t c k s r e n o t e s 2 n o t e s 5 n o t e s 7 n o t e s 3 t c k s r x n o t e s 4 t x s t m r d t c k e s r n o t e s : 1 . s t a r t i n g w i t h i d l e s t a t e 2 . e n t e r s r 3 . c h a n g e f r e q u e n c y 4 . c l o c k m u s t b e s t a b l e t c k s r x 5 . e x i t s r 6 . s e t d l l o n b y m r 1 a 0 = 0 7 . s t a r t d l l r e s e t b y m r 0 a 8 = 1 8 . u p d a t e m o d e r e g i s t e r s 9 . a n y v a l i d c o m m a n d o d t : s t a t i c l o w i n c a s e r t t _ n o m a n d r t t _ w r i s e n a b l e d , o t h e r w i s e s t a t i c l o w o r h i g h n o t e s 6 n o t e s 8 t d l l k o d t l o f f + 1 * t c k t m r d n o t e s 9
1gb ddr3l C as4c128m8d3l confidential 36 rev. 2 . 0 a ug . / 20 1 4 ? jitter notes note 1. unit tck(avg) represents the actual tck(avg) of the input clock under operation. unit nck represents one clock cycle of the input clock, counting the actual clock edges.ex) tmrd = 4 [nck] means; if one mode register set command is registered at tm, another mode register set command may be registered at tm+4, even if (tm+4 - tm) is 4 x tck(avg) + terr(4per),min. n ote 2 . these parameters are measured from a command/address signal (cke, cs#, ras#, cas#, we#, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the cl ock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not. n ote 3 . these parameters are measured from a data strobe signal (dqs, dqs#) crossing to its respective clock signal (ck, c k#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. n ote 4 . these parameters are measured from a data signal (dm, dq0, dq1, etc.) transition edge to its respective data strobe signal (dqs, dqs#) crossing. n ote 5 . for these parameters, the ddr3 l sdram device supports tnparam [nck] = ru{ tparam [ns] / tck(avg) [ns ] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. n ote 6 . when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper),act of the input clock, where 2 <= m <= 12 . (output deratings are relative to the sdram input clock.) n ote 7 . when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per),act of the input clock. (output deratings are relative to the sdram input cl ock.) table 21 . input clock jitter spec parameter parameter symbol - 12 unit min . max . clock period jitter t jit (per) - 70 70 p s clock period jitter during dll locking period t jit (per,lck) - 60 60 p s cycle to cycle clock period jitter t jit (cc) 14 0 p s cycle to cycle clock period jitter during dll locking period t jit (cc,lck) 120 p s cumulative error across 2 cycles t err (2per) - 103 103 p s cumulative error across 3 cycles t err (3per) - 122 122 p s cumulative error across 4 cycles t err (4per) - 136 1 36 p s cumulative error across 5 cycles t err (5per) - 147 147 p s cumulative error across 6 cycles t err ( 6 per) - 155 155 p s cumulative error across 7 cycles t err ( 7 per) - 163 163 p s cumulative error across 8 cycles t err ( 8 per) - 169 169 p s cumulative error across 9 cycles t err ( 9 per) - 175 175 p s cumulative error across 10 cycles t err ( 10 per) - 180 180 p s cumulative error across 11 cycles t err ( 11 per) - 184 184 p s cumulative error across 12 cycles t err ( 12 per) - 188 188 p s cumulative error across n cycles, n =1 3 ...50, inclusive t err ( n per) t err ( n per) min = (1+0.68ln(n)) * t jit (per) min t err ( n per) max = (1+0.68ln(n)) * t jit (per) max p s
1gb ddr3l C as4c128m8d3l confidential 37 rev. 2 . 0 a ug . / 20 1 4 input clock frequency change once the ddr3l sdram is initialized, the ddr3l sdram requires the clock to be stable during almost all states of normal operation. this means once the clock frequency has been set and is to be in the stable state, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and ssc (spread spectrum clocking) spe cification. the input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self - refresh mode and (2) precharge power - down mode. outside of these two modes, it is illegal to change the clock freque ncy. for the first condition, once the ddr3l sdram has been successfully placed in to self - refresh mode and tcksre has been satisfied, the state of the clock becomes a dont care. once a dont care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tcksrx. when entering and exiting self - refresh mode of the sole purpose of changing the clock frequency , the self - refresh entry and exit specifications must still be met . the ddr3l sdram input clock frequency is allo wed to change only within the minimum and maximum operating frequency specified for the particular speed grade. the second condition is when the ddr3l sdram is in precharge power - down mode (either fast exit mode or slow exit mode). if the rtt_nom feature was enabled in the mode register prior to entering precharge power down mode, the odt signal must continuously be registered low ensuring rtt is in an off state. if the rtt_nom feature was disabled in the mode register prior to entering precharge power dow n mode, rtt will remain in the off state. the odt signal can be registered either low or high in this case. a minimum of tcksre must occur after cke goes low before the clock frequency may change. the ddr3l sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. during the input clock frequency change, odt and cke must be held at stable low levels. once the input clock frequency is changed, stable new clocks must be p rovided to the dram tcksrx before precharge power down may be exited; after precharge power down is exited and txp has expired, the dll must be reset via mrs. depending on the new clock frequency additional mrs commands may need to be issued to appropriate ly set the wr, cl, and cwl with cke continuously registered high. during dll re - lock period, odt must remain low and cke must remain high. after the dll lock time, the dram is ready to operate with new clock frequency.
1gb ddr3l C as4c128m8d3l confidential 38 rev. 2 . 0 a ug . / 20 1 4 figure 1 2 . change frequency during precharge power - down c k # t 1 t 2 t a 0 t b 0 t c 0 t c 1 t d 0 t d 1 t e 0 t 0 a d d r e s s c k t e 1 c o m m a n d o d t n o p n o p n o p n o p n o p m r s n o p v a l i d d l l r e s e t h i g h - z h i g h - z d q s # d q s d q d m n o t e s 1 . a p p l i c a b l e f o r b o t h s l o w e x i t a n d f a s t e x i t p r e c h a r g e p o w e r - d o w n . 2 . t a o f p d a n d t a o f m u s t b e s t a t i s f i e d a n d o u t p u t s h i g h - z p r i o r t o t 1 ; r e f e r t o o d t t i m i n g s e c t i o n f o r e x a c t r e q u i r e m e n t s 3 . i f t h e r t t _ n o m f e a t u r e w a s e n a b l e d i n t h e m o d e r e g i s t e r p r i o r t o e n t e r i n g p r e c h a r g e p o w e r d o w n m o d e , t h e o d t s i g n a l m u s t c o n t i n u o u s l y b e r e g i s t e r e d l o w e n s u r i n g r t t i s i n a n o f f s t a t e , a s s h o w n i n f i g u r e 1 3 . i f t h e r t t _ n o m f e a t u r e w a s d i s a b l e d i n t h e m o d e r e g i s t e r p r i o r t o e n t e r i n g p r e c h a r g e p o w e r d o w n m o d e , r t t w i l l r e m a i n i n t h e o f f s t a t e . t h e o d t s i g n a l c a n b e r e g i s t e r e d e i t h e r l o w o r h i g h i n t h i s c a s e . t c h t c l t c k t c k s r e t c h b t c l b t c k b t c h b t c l b t c k b t c h b t c l b t c k b t c k s r x t c k e c k e t i h t i s v a l i d t x p e n t e r p r e c h a r g e p o w e r - d o w n m o d e t c p d e d p r e v i o u s c l o c k f r e q u e n c y n e w c l o c k f r e q u e n c y t a o f p d / t a o f f r e q u e n c y c h a n g e e x i t p r e c h a r g e p o w e r - d o w n m o d e t d l l k d o n ' t c a r e i n d i c a t e s a b r e a k i n t i m e s c a l e t i h t i s t i h t i s
1gb ddr3l C as4c128m8d3l confidential 39 rev. 2 . 0 a ug . / 20 1 4 ? write leveling for better signal integrity, ddr3l memory adopted fly by topology for the commands, addresses, control signals, an d clocks. the fly by topology has benefits from red ucing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every dram on dimm. it makes it difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the controller should s upport write leveling in ddr3l sdram to compensate the skew. the memory controller can use the write leveling feature and feedback from the ddr3l sdram to adjust the dqs C dqs# to ck C ck# relationship. the memory controller involved in the leveling mu st have adjustable delay setting on dqs C dqs# to align the rising edge of dqs C dqs# with that of the clock at the dram pin. dram asynchronously feeds back ck C ck# , sampled with the rising edge of dqs C dqs# , through the dq bus. the controller repeatedly delays dqs C dqs# until a transition from 0 to 1 is detected. the dqs C dqs# delay established though this exercise would ensure tdqss specification. besides tdqss, tdss, and tdsh specification also needs to be fulfilled. one way to achieve this is to com bine the actual tdqss in the application with an appropriate duty cycle and jitter on the dqs - dqs# signals. depending on the actual tdqss in the application, the actual values for tdqsl and tdqsh may have to be better than the absolute limits provided in ac timing parameters section in order to satisfy tdss and tdsh specification. dqs/ dqs# driven by the controller during leveling mode must be determined by the dram based on ranks populated. similarly, the dq bus driven by the dram must also be terminate d at the controller. one or more data bits should carry the leveling feedback to the controller across the dram configurations x8. therefore, a separate feedback mechanism should be available for each byte lane. figure 1 3 . write leveling concept c k # t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 0 c k d i f f _ d q s d q s o u r c e d e s t i n a t i o n t 0 t 1 t 2 t 3 t 4 t 5 t 6 t n c k # c k d i f f _ d q s 0 0 d q d i f f _ d q s 1 1 p u s h d q s t o c a p t u r e 0 - 1 t r a n s i t i o n 0 o r 1 0 o r 1 0 1
1gb ddr3l C as4c128m8d3l confidential 40 rev. 2 . 0 a ug . / 20 1 4 ? dram setting for write leveling and dram termination unction in that mode dram enters into write leveling mode if a7 in mr1 set high and after finishing leveling, dram exits from write leveling mode if a7 in mr1 set low . note that in write leveling mode, only dqs/ dqs# terminations are activated and deactivated via odt pin not like normal operation. table 2 2 . dram termination function in the leveling mode odt pi n at dram dqs, dqs# termination dqs termination de - asserte d off off asserted on off note 1 : in write leveling mode with its output buffer disabled (mr1[bit7]=1 with mr1[bit12]=1) all rtt_nom se ttings are allowed; in write leveling mode with its output buffer enabled (mr1[bit7]=1 with mr1[bit12]=0) only rtt_no m settings of rzq/2, rzq/4, and rzq/6 are allowed. ? procedure description memory controller initiates leveling mode of all drams by setting bit 7 of mr1 to 1. with entering write leveling mode, the dq pins are in undefined driving mode. during write level ing mode, only nop or deselect commands are allowed. as well as an mrs command to exit write leveling mode. since the controller levels one rank at a time, the output of other rank must be disabled by setting mr1 bit a12 to 1. controller may assert odt aft er tmod, time at which dram is ready to accept the odt signal. controller may drive dqs low and dqs# high after a delay of twldqsen, at which time dram has applied on - die termination on these signals. after tdqsl and twlmrd controller provides a single dqs , dqs# edge which is used by the dram to sample ck C ck# driven from controller. twlmrd(max) timing is controller dependent. dram samples ck C ck# status with rising edge of dqs and provides feedback on all the dq bits asynchronously after twlo timing. th ere is a dq output uncertainty of twloe defined to allow mismatch on dq bits; there are no read strobes (dqs/dqs) needed for these dqs. controller samples incoming dq and decides to increment or decrement dqs C dqs# delay setting and launches the next dqs/ dqs# pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the controller locks dqs C dqs# delay setting and write leveling is achieved for the device.
1gb ddr3l C as4c128m8d3l confidential 41 rev. 2 . 0 a ug . / 20 1 4 figure 14 . timing details of write levelin g sequence ( dqs C dqs# is capturing ck C ck# low at t1 and ck C ck# high at t2 ) t w l m r d d o n ' t c a r e t i m e b r e a k n o p m r s n o p n o p n o p n o p n o p n o p n o p n o p n o p t w l s t w l h t 1 t w l s t w l h t 2 n o p n o t e s 1 n o t e s 2 t w l d q s e n t d q s l n o t e s 6 t d q s h n o t e s 6 t d q s l n o t e s 6 t d q s h n o t e s 6 c k # c k c o m m a n d o d t d i f f _ d q s p r i m e d q n o t e s 5 n o t e s 4 o n e p r i m e d q : n o t e s 3 l a t e p r i m e d q s e a r l y p r i m e d q s a l l d q s a r e p r i m e : n o t e s 3 n o t e s 3 l a t e r e m a i n i n g d q s e a r l y r e m a i n i n g d q s t w l o t w l o t w l o t w l o e t w l o t w l o e t w l o t m o d t w l o t w l m r d t w l o t w l o t w l o e u n d e f i n e d d r i v i n g m o d e n o t e s 1 . m r s : l o a d m r 1 t o e n t e r w r i t e l e v e l i n g m o d e . 2 . n o p : n o p o r d e s e l e c t . 3 . d r a m h a s t h e o p t i o n t o d r i v e l e v e l i n g f e e d b a c k o n a p r i m e d q o r a l l d q s . i f f e e d b a c k i s d r i v e n o n l y o n o n e d q , t h e r e m a i n i n g d q s m u s t b e d r i v e n l o w , a s s h o w n i n a b o v e f i g u r e , a n d m a i n t a i n e d a t t h i s s t a t e t h r o u g h o u t t h e l e v e l i n g p r o c e d u r e . 4 . d i f f _ d q s i s t h e d i f f e r e n t i a l d a t a s t r o b e ( d q s , d q s # ) . t i m i n g r e f e r e n c e p o i n t s a r e t h e z e r o c r o s s i n g s . d q s i s s h o w n w i t h s o l i d l i n e , d q s # i s s h o w n w i t h d o t t e d l i n e . 5 . c k , c k # : c k i s s h o w n w i t h s o l i d d a r k l i n e , w h e r e a s c k # i s d r a w n w i t h d o t t e d l i n e . 6 . d q s , d q s # n e e d s t o f u l f i l l m i n i m u m p u l s e w i d t h r e q u i r e m e n t s t d q s h ( m i n ) a n d t d q s l ( m i n ) a s d e f i n e d f o r r e g u l a r w r i t e s ; t h e m a x p u l s e w i d t h i s s y s t e m d e p e n d e n t .
1gb ddr3l C as4c128m8d3l confidential 42 rev. 2 . 0 a ug . / 20 1 4 ? write leveling mode exit the following sequence describes how write leveling mode should be exited: 1. after the last rising strobe edge (see ~t 0), stop driving the strobe signals (see ~tc0). note: from now on, dq pins are in undefined driving mode, and will remain undefined, until tmod after the respective mr command (te1). 2. drive odt pin low (tis must be satisfied) and keep it low (see tb0). 3 . after the rtt is switched off, disable write level mode via mrs command (see tc2). 4. after tmod is satisfied (te1), any valid command may be registered. (mr commands may be issued after tmrd (td1). figure 15 . timing de tails of write leveling exit ? extended temperature usage users should refer to the dram supplier data sheet and/or the dimm spd to determine if ddr3l sdram devices support the following options or requirements referred to in this material: 1. auto self - refre sh supported 2 . extended temperature range supported 3 . double refresh required for operation in the extended temperature range (applies only for devices supporting the extended temperature range) ? auto self - refresh mode - asr mode ddr3l sdram provides an auto - refresh mode (asr) for application ease. asr mode is enabled by setting mr2 bit a6=1 and mr2 bit a7=0. the dram will manage self - refresh entry in either the normal or extended temperature ranges . in this mode, the dram will also manage self - refresh po wer consumption when the dram operating temperature changes, lower at low temperatures and higher at high temperatures. if the asr option is not supported by dram, mr2 bit a6 must set to 0. if the asr option is not enabled (mr2 bit a6=0), the srt bit (mr2 bit a7) must be manually programmed with the operating temperature range required during self - refresh operation. support of the asr option does not automatically imply support of the extended temperature range. d o n ' t c a r e t i m e b r e a k n o p n o p n o p n o p n o p n o p n o p m r s n o p v a l i d n o p v a l i d t w l o t a o f m i n u n d e f i n e d d r i v i n g m o d e t 1 t 2 t a 0 t b 0 t c 0 t c 1 t c 2 t 0 t d 0 t d 1 t e 0 t e 1 n o t e s : 1 . t h e d q r e s u l t = 1 b e t w e e n t a 0 a n d t c 0 i s a r e s u l t o f t h e d q s , d q s # s i g n a l s c a p t u r i n g c k h i g h j u s t a f t e r t h e t 0 s t a t e . m r 1 v a l i d v a l i d t m r d r t t _ n o m r e s u l t = 1 t r a n s i t i o n i n g t a o f m a x t i s o d t l o f f t m o d c k # c k c o m m a n d a d d r e s s o d t r t t _ d q s _ d q s # d q d q s _ d q s # r t t _ d q n o t e s 1
1gb ddr3l C as4c128m8d3l confidential 43 rev. 2 . 0 a ug . / 20 1 4 ? self - refresh temperature range - srt sr t applies to devices supporting extended temperature range only. if asr=0, the self - refresh temperature (srt) range bit must be programmed to guarantee proper self - refresh operation. if srt=0, then the dram will set an appropriate refresh rate for self - ref resh operation in the normal temperature range. if srt=1, then the dram will set an appropriate, potentially different, refresh rate to allow self - refresh operation in either the normal or extended temperature ranges. the value of the srt bit can effect se lf - refresh power consumption, please refer to idd table for details. table 2 3 . self - refresh mode summary mr2 a[6] mr2 a[7] self - refresh operation allowed operating temperature range for self - refresh mode 0 0 self - refresh rate appropriate for the normal t emperature range normal (0 ~ 85c) 0 1 self - refresh appropriate for either the normal or extended temperature ranges. the dram must support extended temperature range. the value of the srt bit can effect self - refresh power consumption, please refer to the idd table for details. normal and extended (0 ~ 95c) 1 0 asr enabled (for devices supporting asr and normal temperature range).self - refresh power consumption is temperature dependent. normal (0 ~ 85c) 1 0 asr enabled (for devices supporting asr and exten ded temperature range).self - refresh power consumption is temperature dependent. normal and extended (0 ~ 95c) 1 1 illegal ? active command the active command is used to open (or activate) a row in a particular bank for subsequent access. the value on th e ba0 - ba2 inputs selects the bank, and the addresses provided on inputs a0 - a1 3 selects the row. these rows remain active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. ? precharge command the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row activation a specified time (trp) after the precharge co mmand is issued, except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. once a b ank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is allowed if there is no open row in that bank (idle bank) or if the previously open row is already i n the process of precharging. however, the precharge period will be determined by the last precharge command issued to the bank.
1gb ddr3l C as4c128m8d3l confidential 44 rev. 2 . 0 a ug . / 20 1 4 read operation ? read burst operation durin g a read or write command ddr3l will support bc4 and bl8 on the fly using address a 12 during the read or write (auto precharge can be enabled or disabled). a12=0, bc4 (bc4 = burst chop, tccd=4) a12=1, bl8 a12 will be used only for burst length control, not a column address. figure 16 . read burst operation rl=5 (al=0, cl=5, bl=8) figure 17 . read burst operation rl=9 (al=4, cl=5, bl=8) d o n ' t c a r e n o p r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b l 8 , r l = 5 , a l = 0 , c l = 5 . 2 . d o u t n = d a t a - o u t f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 0 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 b a n k , c o l n t r a n s i t i o n i n g d a t a t r p r e t r p s t d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 r l = a l + c l c l = 5 c k # c k d q s , d q s # d q n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d d o n ' t c a r e n o p r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b l 8 , r l = 9 , a l = ( c l - 1 ) , c l = 5 . 2 . d o u t n = d a t a - o u t f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 0 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 b a n k , c o l n t r a n s i t i o n i n g d a t a t r p r e d o u t n d o u t n + 1 d o u t n + 2 r l = a l + c l a l = 4 c l = 5 c k # c k d q s , d q s # d q n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d
1gb ddr3l C as4c128m8d3l confidential 45 rev. 2 . 0 a ug . / 20 1 4 read timing definitions read timing is shown in the following figure and is applied when the dll is enabled and locked. rising data strobe edge parameters: tdqsck min/max describes the allowed range for a rising data strobe edge relative to ck, ck# . tdqsck is the actual position of a rising strobe edge relative to ck, ck# . tqsh describes the dqs, dqs# differential output high time. tdqsq des cribes the latest valid transition of the associated dq pins. tqh describes the earliest invalid transition of the associated dq pins. falling data strobe edge parameters: tqsl describes the dqs, dqs# differential output low time. tdqsq describes the late st valid transition of the associated dq pins. tqh describes the earliest invalid transition of the associated dq pi ns. tdqsq; both rising/falling edges of dqs, no tac defined. figure 18 . read timing definition t d q s c k t d q s c k , m i n c k # c k t d q s c k , m a x t d q s c k , m a x r i s i n g s t r o b e r e g i o n t d q s c k , m i n d q s # d q s t d q s c k t q s h t q s l r i s i n g s t r o b e r e g i o n a s s o c i a t e d d q p i n s t q h t q h t d q s q t d q s q
1gb ddr3l C as4c128m8d3l confidential 46 rev. 2 . 0 a ug . / 20 1 4 ? read timing; clock to data strobe relationship clock to data strobe relationship is shown in the following figure and is applied when the dll is enabled and locked. rising data strobe edge parameters: tdqsck min/max describes the allowed range for a r ising data strobe edge relative to ck and ck# . tdqsck is the actual position of a rising strobe edge relative to ck and ck# . tqsh describes the data strobe high pulse width. falling data strobe edge parameters: tqsl describes the data strobe low pulse widt h. figure 19 . clock to data strobe relationship n o t e s : 1 . w i t h i n a b u r s t , r i s i n g s t r o b e e d g e i s n o t n e c e s s a r i l y f i x e d t o b e a l w a y s a t t d q s c k ( m i n ) o r t d q s c k ( m a x ) . i n s t e a d , r i s i n g s t r o b e e d g e c a n v a r y b e t w e e n t d q s c k ( m i n ) a n d t d q s c k ( m a x ) . 2 . n o t w i t h s t a n d i n g n o t e 1 , a r i s i n g s t r o b e e d g e w i t h t d q s c k ( m a x ) a t t ( n ) c a n n o t b e i m m e d i a t e l y f o l l o w e d b y a r i s i n g s t r o b e e d g e w i t h t d q s c k ( m i n ) a t t ( n + 1 ) . t h i s i s b e c a u s e o t h e r t i m i n g r e l a t i o n s h i p s ( t q s h , t q s l ) e x i s t : i f t d q s c k ( n + 1 ) < 0 : t d q s c k ( n ) < 1 . 0 t c k - ( t q s h m i n + t q s l m i n ) - | t d q s c k ( n + 1 ) | 3 . t h e d q s , d q s # d i f f e r e n t i a l o u t p u t h i g h t i m e i s d e f i n e d b y t q s h a n d t h e d q s , d q s # d i f f e r e n t i a l o u t p u t l o w t i m e i s d e f i n e d b y t q s l . 4 . l i k e w i s e , t l z ( d q s ) m i n a n d t h z ( d q s ) m i n a r e n o t t i e d t o t d q s c k m i n ( e a r l y s t r o b e c a s e ) a n d t l z ( d q s ) m a x a n d t h z ( d q s ) m a x a r e n o t t i e d t o t d q s c k m a x ( l a t e s t r o b e c a s e ) . 5 . t h e m i n i m u m p u l s e w i d t h o f r e a d p r e a m b l e i s d e f i n e d b y t r p r e ( m i n ) . 6 . t h e m a x i m u m r e a d p o s t a m b l e i s b o u n d b y t d q s c k ( m i n ) p l u s t q s h ( m i n ) o n t h e l e f t s i d e a n d t h z d s q ( m a x ) o n t h e r i g h t s i d e . 7 . t h e m i n i m u m p u l s e w i d t h o f r e a d p o s t a m b l e i s d e f i n e d b y t r p s t ( m i n ) . 8 . t h e m a x i m u m r e a d p r e a m b l e i s b o u n d b y t l z d q s ( m i n ) o n t h e l e f t s i d e a n d t d q s c k ( m a x ) o n t h e r i g h t s i d e . c l k # c l k t l z ( d q s ) m i n d q s , d q s # l a t e s t r o b e d q s , d q s # e a r l y s t r o b e t r p r e t l z ( d q s ) m a x t d q s c k ( m i n ) t q s h t q s l t d q s c k ( m i n ) t q s h t q s l t q s h t q s l t d q s c k ( m i n ) t d q s c k ( m i n ) t r p s t t h z ( d q s ) ( m i n ) b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7 t d q s c k ( m a x ) t r p r e t q s h t q s l t d q s c k ( m a x ) t q s h t q s l t q s h t q s l t d q s c k ( m a x ) t d q s c k ( m a x ) t r p s t t h z ( d q s ) ( m a x ) b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7 r l m e a s u r e d t o t h i s p o i n t
1gb ddr3l C as4c128m8d3l confidential 47 rev. 2 . 0 a ug . / 20 1 4 ? read timing; data strobe to data relationship the data strobe to data relationship is shown in the following figure and is applied when the dll and enabled and l ocked. rising data strobe edge parameters: - tdqsq describes the latest valid transition of the associated dq pins. - tqh describes the earliest invalid transition of the associated dq pins. falling data strobe edge parameters: - tdqsq describes the latest valid transition of the associated dq pins. - tqh describes the earliest invalid transition of the associated dq pins. - tdqsq; both rising/falling edges of dqs, no tac defined tdqsq; both rising/falling edges of dqs, no tac defined . figure 2 0 . data str obe to data relationship t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 0 t 1 0 r l = a l + c l n o p r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p b a n k , c o l n t d q s q ( m a x ) d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 c k # a d d r e s s c k c o m m a n d d q s , d q s # d q ( l a s t d a t a v a l i d ) a l l d q s c o l l e c t i v e l y d q ( f i r s t d a t a n o l o n g e r v a l i d ) t r p r e t q h t q h t d q s q ( m a x ) t r p s t n o t e s 3 n o t e s 4 n o t e s 2 n o t e s 2 n o t e s : 1 . b l = 8 , r l = 5 ( a l = 0 , c l = 5 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 0 . 5 . o u t p u t t i m i n g s a r e r e f e r e n c e d t o v d d q / 2 , a n d d l l o n f o r l o c k i n g . 6 . t d q s q d e f i n e s t h e s k e w b e t w e e n d q s , d q s # t o d a t a a n d d o e s n o t d e f i n e d q s , d q s # t o c l o c k . 7 . e a r l y d a t a t r a n s i t i o n s m a y n o t a l w a y s h a p p e n a t t h e s a m e d q . d a t a t r a n s i t i o n s o f a d q c a n v a r y ( e i t h e r e a r l y o r l a t e ) w i t h i n a b u r s t . d o n ' t c a r e t r a n s i t i o n i n g d a t a d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7
1gb ddr3l C as4c128m8d3l confidential 48 rev. 2 . 0 a ug . / 20 1 4 write operation ? ddr3l burst operation during a read or write command, ddr3l will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). a12=0, bc4 (bc4 = burst chop, tccd=4) a12=1, bl8 a12 is used only for burst length control, not as a column addres s. ? write timing violations generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to ma ke sure the dram works properly. however, it is desirable for certain minor violations that the dram is guaranteed not to hang up and errors be limited to that particular operation. for the following, it will be assumed that there are no timing violation s with regard to the write command itself (including odt, etc.) and that it does satisfy all timing requirements not mentioned below. ? data setup and hold violations should the strobe timing requirements (tds, tdh) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. subsequent reads from that location might result in unpredictable read data, however, the dram will work properly otherwise. ? strobe to strobe and strobe to clock violations should the strobe timing requirements (tdqsh, tdqsl, twpre, twpst) or the strobe to clock timing requirements (tdss, tdsh, tdqss) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. subsequent reads from that location might result in unpredictable read data, however the dram will work properly otherwise. ? write timing parameters this drawing is for example only to enumerate the strobe edges that belong to a write burst. no actual timing violations are shown here. for a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge ). ? refresh command the refresh command (ref) is used during normal operation of the ddr3l sdrams. this command is not persistent, so it must be issued each time a refresh is required. the ddr3l sdram requires refresh cycles at an average periodic interval of trefi. when cs# , ras# , and cas# are held low and we# high at the rising edge of the clock, the chip enters a refresh cycle. all banks of the sdram must be precharged and idle for a minimum of the precharge time trp(min) before the refresh command can be applied. the refre sh addressing is generated by the internal refresh controller. this makes the address bits dont care during a refresh command. an internal address counter suppliers the address during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the refresh command and the next valid command, except nop or des, must be greater than or equal to the minim um refresh cycle time trfc(min) . in general, a refresh command needs to be issued to the ddr3l sdram regularly every trefi interval. to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh inter val is provided. a maximum of 8 refresh commands can be postponed during operation of the ddr3l sdram, meaning that at no point in time more than a total of 8 refresh commands are allowed to be postponed. in case that 8 refresh commands are postponed in a row, the resulting maximum interval between the surrounding refresh commands is limited to 9 x trefi. a maximum of 8 additional refresh commands can be issued in advance (pulled in), with each one reducing the number of regular refresh commands required later by one. note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh command is limited to 9 x trefi . before entering self - refresh mode, all postponed refresh commands must be executed.
1gb ddr3l C as4c128m8d3l confidential 49 rev. 2 . 0 a ug . / 20 1 4 ? self - refresh operation the self - refresh command can be u sed to retain data in the ddr3l sdram, even if the reset of the system is powered down. when in t he self - refres h mode, the ddr3l sdram retains data without external clocking. the ddr3l sdram device has a built - in timer to accommodate self - refresh operation. the self - refresh entry (sre) command is defined by having cs # , ras# , cas# , and cke held low with we # high at the rising edge of the clock. before issuing the self - refr eshing - entry command, the ddr3l sdram must be idle with all bank precharge state with trp satisfied. also, on - die termination must be turned off before issuing self - refresh - entry command, by either registering odt pin low odtl + 0.5tck prior to the self - refresh entry command or using mrs to mr1 command. once the self - refresh entry command is registered, cke must be held low to keep the device in self - refresh mode. during normal operation (dll on), mr1 (a0=0), the dll is automatically disabled upon entering self - refresh and is automatically enabled (including a dll - reset) upon exiting self - refresh. when the ddr3l sdram has entered self - refresh mode, all of the external control signals, except cke a nd reset# , are dont care. for proper self - refresh operation, all power supply and reference pins (vdd, vddq, vss, vssq, vrefca, and vrefdq) must be at valid levels. the dram initiates a minimum of one refresh command internally within tcke period once i t enters self - refresh mode. the clock is internally disabled during self - refresh operation to save power. the minimum time that the ddr3l sdram must remain in self - refresh mode is tcke. the user may change the external clock frequency or halt the external clock tcksre after self - refresh entry is registered; however, the clock must be restarted and stable tcksrx before the device can exit self - refresh mode. the procedure for exiting self - refresh requires a sequence of events. first, the clock must be stable prior to cke going back high. once a self - refresh exit command (srx, combination of cke going high and either nop or deselect on command bus) is registered, a delay of at least txs must be satisfied before a valid command not requiring a locked dll can be issued to the device to allow for any internal refresh in progress. before a command which requires a locked dll can be applied, a delay of at least txsdll and applicable zqcal function requirements [tbd] must be satisfied. before a command that requires a locked dll can be applied, a delay of at least txsdll must be satisfied. depending on the system environment and the amount of time spent in self - refresh, zq calibration command may be required to compensate for the voltage and temperature drift as des cribed in zq calibration c ommands . to issue zq calibration commands, applicable timing requirements must be satisfied. cke must remain high for the entire self - refresh exit period txsdll for proper operation except for self - refresh re - entry. upon exit f rom self - refresh, the ddr3l sdram can be put back into self - refresh mode after waiting at least txs period and issuing one refresh command (refresh period of trfc). nop or deselect commands must be registered on each positive clock edge during the self - ref resh exit interval txs. odt must be turned off during txsdll. the use of self - refresh mode instructs the possibility that an internally times refresh event can be missed when cke is raised for exit from self - refresh mode. upon ex it from self - refresh, the ddr3l sdram requires a minimum of one extra refresh command before it is put back into self - refresh mode.
1gb ddr3l C as4c128m8d3l confidential 50 rev. 2 . 0 a ug . / 20 1 4 power - down modes ? power - down entry and exit power - down is synchronously entered when cke is registered low (along with nop or deselect command). cke is not allowed to go low while mode register set command, mpr operations, zqcal operations, dll locking or read/write operation are in progress. cke is allowed to go low while any of other operation such as row activation, precharge or auto precharge and r efresh are in progress, but power - down idd spec will not be applied until finishing those operation. the dll should be in a locked state when power - down is entered for fastest power - down exit timing. if the dll is not locked during power - down entry, the dl l must be reset after exiting power - down mode for proper read operation and synchronous odt operation. dram design provides all ac and dc timing and voltage specification as well proper dll operation with any cke intensive operations as long as dram contro ller complies with dram specifications. during power - down, if all banks are closed after any in progress commands are completed, the device will be in precharge power - down mode; if any bank is open after in progress commands are completed, the device will be in active power - down mode. entering power - down deactivates the input and output buffers, excluding ck, ck, odt, cke , and reset# . to protect dram internal delay on cke line to block the input signals, multiple nop or deselect commands are needed during the cke switch off and cycle(s) after, this timing period are defined as tcpded. cke_low will result in deactivation of command and address receivers after tcpded has expired. table 2 4 . power - down entry definitions status of dram mrs bit a12 dll pd exit relevant parameters active (a bank or more open) don't care on fast txp to any valid command. precharged (all banks precharged) 0 off slow txp to any valid command. since it is in precharge state, commands her e will be act, ar, mrs/emrs, pr or pra. txpdl l to commands who need dll to operate, such as rd, rda or odt control line. precharged (all banks precharged) 1 on fast txp to any valid command. also the dll is disabled upon entering precharge power - down (slow exit mode), but the dll is kept enabled du ring precharge power - down (fast exit mode) or active power - down. in power - down mode, cke low, reset# high, and a stable clock signal must be mainta ined at the inputs of the dd 3 sdram, and odt should be in a valid state but all other input signals are don t care (if reset# goes low during power - down, the dram will be out of pd mode and into reset state). cke low must be maintain until tcke has been satisfied. power - down duration is limited by 9 times trefi of the device. the power - down state is synchronou sly exited when cke is registered high (along with a nop or deselect command).cke high must be maintained until tcke has been satisfied. a valid, executable command can be applied with power - down exit latency, txp and/or txpdll after cke goes high. power - d own exit latency is defined at ac spec table of this datasheet.
1gb ddr3l C as4c128m8d3l confidential 51 rev. 2 . 0 a ug . / 20 1 4 on - die termination (odt) on - die termination (odt) is a feature that enables the dram to enable/disable and turn on/off termination resistance for each dq, dqs, dqs#, and dm for the x8 configu rations (and tdqs, tdqs# for the x8 configuration, when enabled). odt is designed to improve signal integrity of the memory channel by enabling the dram controller to independently turn on/off the dram s internal termination resistance for any grouping of dram devices. odt is not supported during dll disable mode (simple functional representation shown below). the switch is enabled by the internal odt control logic, which uses the external odt ball and other control information. figure 21 . functional repre sentation of odt the switch is enabled by the internal odt control logic, which uses the external odt pin and other control information. the value of rtt is determined by the settings of mode register bits. the odt pin will b e ignored if the mode register mr1 and mr2 are programmed to disable odt and in self - refresh mode. ? odt mode register and odt truth table the odt mode is enabled if either of mr1 {a2, a6, a9} or mr2 {a9, a10} are non - z ero. in this case, the value of rtt i s determined by the settings of those bits. application: controller sends wr command together with odt asserted. one possible application: the rank that is being written to provides termination. dram turns on termination if it sees odt asserted (except od t is disabled by mr) dram does not use any write or read command decode information. table 2 5 . termination truth table odt pin dram termination state 0 o ff 1 on, (off, if disabled by mr1 (a2, a6, a9) and mr2 (a9, a10) in general ) t o o t h e r c i r c u i t r y l i k e r c v , . . . d q , d q s , d m , t d q s o d t v d d q / 2 r t t s w i t c h
1gb ddr3l C as4c128m8d3l confidential 52 rev. 2 . 0 a ug . / 20 1 4 ? synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked. based on th e power - down definition, these modes are: - any bank active with cke high - refresh with cke high - idle mode with cke high - active power down mode (regardless of mr0 bit a12) - precharge power down mode if dll is enabled during precharge power down by mr0 bit a12 the direct odt feature is not supported during dll - off mode. the on - die termination resistors must be disabled by continuously registering the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. in synchronous odt mode, rtt will be turned on odtlon clock cycles after odt is sampled high by a rising clock edge and turned off odtloff clock cycles after odt is registered low by a rising clock edge. the odt latency is tied to the write latency (wl) by : odtlon = wl - 2; odtloff = wl - 2. ? odt latency and posted odt in synchronous odt mode, the additive latency (al) programmed into the mod e registe r (mr1) also applies to the odt signal. the dram internal odt signal is delayed for a number of clock cycles defined by the additive latency (al) relative to the external odt signal. odtlon = cwl + al - 2; odtloff = cwl + al - 2. for details, refe r to ddr3l sdram latency definitions. table 2 6 . odt latency symbol parameter ddr3l - 1600 unit odtlon odt turn on latency wl C 2 = cwl + al - 2 tck odtloff odt turn off latency wl C 2 = cwl + al - 2 tck ? timing parameters in synchronous odt mode, the foll owing timing parameters apply: odtlon, odtloff, taon min/max, taof min/max. minimum rtt turn - on time (taon min) is the point in time when the device leaves high impedance and odt resistance begins to turn on. maximum rtt turn - on time (taon max) is the poi nt in time when the odt resistance is fully on. both are measured from odtlon. minimum rtt turn - off time (taof min) is the point in time when the device starts to turn off the odt resistance. maximum rtt turn off time (taof max) is the point in time when t he on - die termination has reached high impedance. both are measured from odtloff. when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registered by the sdram with odt high, then odt must remain high until odth4 (bl=4) or odth8 (bl=8) after the write command. odth4 and odth8 are measured from odt registered high to odt registered low or from the registration of a write command until odt is registered low . ? odt during reads as the ddr3l sdram cannot terminate and drive a t the same time, rtt must be disabled at least half a clock cycle before the read preamble by driving the odt pin low appropriately. rtt may not be enabled until the end of the post - amble as shown in the following figure. dram turns on the termination when it stops driving which is determined by thz. if dram stops driving early (i.e. thz is early), then taonmin time may apply. if dram stops driving late (i.e. thz is late), then dram complies with taonmax timing. note that odt may be disabled earlier before the read and enabled later after the read than shown in this example in figure 11 . .
1gb ddr3l C as4c128m8d3l confidential 53 rev. 2 . 0 a ug . / 20 1 4 figure 22 . odt must be disabled externally during reads by driving odt low (cl=6; al=cl - 1=5; rl=al+cl=11; cwl=5; odtlon=cwl+al - 2=8; odtloff=cwl+al - 2=8) ? dynamic odt in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3l sdram can be changed without issuing an mrs command. this requirement is supported by the dynamic odt feature as described as follows: functional description the dynamic odt mode is enabled if bit (a9) or (a10) of mr2 is set to 1. the function is described as follows: two rtt values are available: rtt_nom and rtt_wr. - the value for rtt_nom is preselected via bits a[9,6,2] in mr1. - the value for rtt_wr is preselected via bits a[10,9] in mr2. during operation without write commands, the termination is controlled as follows: - nominal termination strength rtt_nom is selected. - te rmination on/off timing is controlled via odt pin and latencies odtlon and odtloff. when a write comma nd (wr, wra, wrs4, wrs8, wras4, wras8) is registered, and if dynamic odt is enabled, the termination is controlled as follows: - a latency odtlcnw after the write command, termination strength rtt_wr is selected. - a latency odtlcwn8 (for bl8, fixed by mrs or selected otf) or odtlcwn4 (for bc4, fixed by mrs or selected otf) after the write command, termination strength rtt_nom is selected. - termination on /off timing is controlled via odt pin and odtlon, odtloff. the following table shows latencies and timing parameters which are relevant for the on - die termination control in dynamic odt mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2 [a10,a9 = [0,0], to disable dynamic odt externally. when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registered by the sdram with odt high, then odt must remain high until o dth4 (bl=4) or odth8 (bl=8) after the write command. odth4 and odth8 are measured from odt registered high to odt registered low or from the registration of write command until odt is register low. n o p r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k t 1 2 t 1 3 t 1 4 n o p n o p n o p d o n ' t c a r e t r a n s i t i o n i n g d a t a t 1 5 n o p o d t t 1 6 t 1 7 n o p n o p o d t l o n = c w l + a l - 2 o d t l o f f = c w l + a l - 2 r l = a l + c l t a o f ( m i n ) t a o f ( m a x ) t a o n ( m a x ) v a l i d r t t r t t _ n o m r t t _ n o m d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d q c o m m a n d a d d r e s s d q s , d q s # d i n b + 7
1gb ddr3l C as4c128m8d3l confidential 54 rev. 2 . 0 a ug . / 20 1 4 table 2 7 . latencies and timing parameters relevant f or dynamic odt name and description abbr. defined from defined to definition for all ddr3l speed pin unit odt turn - on latency odtlon registering external odt signal high turning termination on odtlon=wl - 2 tck odt turn - off latency odtloff registering exte rnal odt signal low turning termination off odtloff=wl - 2 tck odt latency for changing from rtt_nom to rtt_wr odtlcnw registering external write command change rtt strength from rtt_nom to rtt_wr odtlcnw=wl - 2 tck odt latency for change from rtt_wr to rtt_ nom (bl=4) odtlcwn4 registering external write command change rtt strength from rtt_wr to rtt_nom odtlcwn4=4+odtloff tck odt latency for change from rtt_wr to rtt_nom (bl=8) odtlcwn8 registering external write command change rtt strength from rtt_wr to rt t_nom odtlcwn8=6+odtloff tck (avg) minimum odt high time after odt a ssertion odth4 registering odt high odt registered low odth4=4 tck (avg) minimum odt high time after write (bl=4) odth4 registering write with odt high odt registered low odth4=4 tck (av g) minimum odt high time after write (bl=8) odth8 registering write with odt high odt register low odth8=6 tck (avg) rtt change skew tadc odtlcnw odtlcwn rtt valid tadc(min)=0.3tck(avg) tadc(max)=0.7tck(avg) tck (avg) note 1 : taof,nom and tadc,nom are 0.5tck (effectively adding half a clock cycle to odtloff, odtcnw, and odtlcwn) ? asynchronous odt mode asynchronous odt mode is selected when dram runs in dllon mode, but dll is temporarily disabled (i.e. frozen) in precharge power - down (by mr0 bit a12). b ased on the power down mode definitions, this is currently precharge power down mode if dll is disabled during precharge power down by mr0 bit a12. in asynchronous odt timing mode, internal odt command is not delayed by additive latency (al) relative to th e external odt command. in asynchronous odt mode, the following timing parameters apply: taonpd min/max, taofpd min/max. minimum rtt turn - on time (taonpd min) is the point in time when the device termination circuit leaves high impedance state and odt resi stance begins to turn on. maximum rtt turn on time (taonpd max) is the point in time when the odt resistance is fully on. taonpdmin and taonpdmax are measured from odt being sampled high. minimum rtt turn - off time (taofpdmin) is the point in time when the devices termination circuit starts to turn off the odt resistance. maximum odt turn off time (taofpdmax) is the point in time when the on - die termination has reached high imped ance. taofpdmin and taofpdmax are measured from odt being sample low. table 2 8 . odt timing parameters for power down (with dll frozen) entry and exit description min max odt to rtt turn - on delay min{ odtlon * tck + taonmin; taonpdmin } min{ (wl - 2) * tck + taonmin; taonpdmin } max{ odtlon * tck + taonmax; taonpdmax } max{ (wl - 2) * tck + taonmax; taonpfmax } odt to rtt turn - off delay min{ odtloff * tck + taofmin; taofpdmin } min{ (wl - 2) * tck + taofmin; taofpdmin } max{ odtloff * tck + taofmax; taofpdmax } max{ (wl - 2) * tck + taofmax; taofpdmax } tanpd wl - 1
1gb ddr3l C as4c128m8d3l confidential 55 rev. 2 . 0 a ug . / 20 1 4 ? synchronou s to asynchronous odt mode transition during power - down entry if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to 0, there is a transition period around power down entry, where the ddr3l sdram may show either synchronous or asynchronous odt behavior. the transition period is defined by the pa rameters tanpd and tcpded(min). tanpd is equal to (wl - 1) and is counted backwards in time from the clock cycle whe re cke is first registered low. tcpded(min) starts with th e clock cycle where cke is first registered low. the transition period begins with the starting point of tanpd and terminates at the end point of tcpded(min). if there is a refresh command in progress while cke goes low, then the transition period ends at the later one of trfc(min) after the refresh command and the end point of tcpded(min). please note that the actual starting point at tanpd is excluded from the transition period, and the actual end point at tcpded(min) and trfc(min, respectively, are inclu ded in the transition period. odt assertion during the transition period may result in an rtt changes as early as the smaller of taonpdmin and (odtlon*tck+taonmin) and as late as the larger of taonpdmax and (odtlon*tck+taonmax). odt de - assertion during the transition period may result in an rtt change as early as the smaller of taofpdmin and (odtloff*tck+taofmin) and as late as the larger of taofpdmax and (odtloff*tck+taofmax). note that, if al has a large value, the range where rtt is uncertain becomes qui te large. the following figure shows the three different cases: odt_a, synchronous behavior before tanpd; odt_b has a state change during the transition period; odt_c shows a state change after the transition period. ? asynchronous to synchronous odt mode transition during power - down exit if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to 0, there is also a transition period around power down exit, where either synchronous or asynchronous response to a change in odt must be expected from the ddr3l sdram. this transition period starts tanpd before cke is first registered high, and ends txpdll after cke is first registered high. tanpd is equal to (wl - 1) and is counted (backwards) from the clock cycle where cke i s first registered high. odt assertion during the transition period may result in an rtt change as early as the smaller of taonpdmin and (odtlon* tck+taonmin) and as late as the larger of taonpdmax and (odtlon*tck+taonmax). odt de - assertion during the tran sition period may result in an rtt change as early as the smaller of taofpdmin and (odtloff*tck+taofmin) and as late as the larger of taofpdmax and (odtoff*tck+taofmax). note that if al has a large value, the range where rtt is uncertain becomes quite larg e. the following figure shows the three different cases: odt_c, asynchronous response before tanpd; odt_b has a state change of odt during the transition period; odt_a shows a state change of odt after the transition period with synchronous response. ? asy nchronous to synchronous odt mode during short cke high and short cke low periods if the total time in precharge power down state or idle state is very short, the transition periods for pd entry and pd exit may overlap. in this case, the response of the dd r3l sdrams rtt to a change in odt state at the input may be synchronous or asynchronous from the state of the pd entry transition period to the end of the pd exit transition period (even if the entry ends later than the exit period). if the total time in i dle state is very short, the transition periods for pd exit and pd entry may overlap. in this case, the response of the ddr3l sdrams rtt to a change in odt state at the input may be synchronous or asynchronous from the state of the pd exit transition perio d to the end of the pd entry transition period. note that in the following figure, it is assumed that there was no refresh command in progress when idle state was entered.
1gb ddr3l C as4c128m8d3l confidential 56 rev. 2 . 0 a ug . / 20 1 4 zq calibration commands ? zq calibration description zq calibration command is used to calibrate dram ron and odt values. ddr3l sdram needs longer time to calibrate output driver and on - die termination circuits at initialization and relatively smaller time to perform periodic calibrations. zqcl command is used to perform the initial cali bration during power - up initialization sequence. this command may be issued at any time by the controller depending on the system environment. zqcl command triggers the calibration engine inside the dram and once calibration is achieved the calibrated valu es are transferred from calibration engine to dram io which gets reflected as updated output driver and on - die termination values. the first zqcl command issued after reset is allowed a timing period of tzqinit to perform the full calibration and the trans fer of values. all other zqcl commands except the first zqcl command issued after reset is allowed a timing period of tzqoper. zqcs command is used to perform periodic calibrations to account for voltage and temperature variations. a shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tzqcs. no other activities should be performed on the dram channel by the controller for the duration of tzqinit, tzqoper, or tzqcs. the quiet time on the dram cha nnel allows calibration of output driver and on - die termination values. once dram calibration is achieved, the dram should disable zq current consumption path to reduce power. all banks must be precharged and trp met before zqcl or zqcs commands are issued by the controller. zq calibration commands can also be issued in parallel to dll lock time when coming out of self refresh. upon self - refresh exit, ddr3 l sdram will not perform an io calibration without an explicit zq calibration command. the earliest pos sible time for zq calibration command (short or long) after self refresh exit is txs. in systems that share the zq resistor between devices, the controller must not allow any overlap of tzqoper, tzqinit, or tzqcs between ranks. figure 2 3 . zq calibration timing ? zq external resistor value, tolerance, and capacitive loading in order to use the zq calibration function, a 240 ohm +/ - 0.1% tolerance external resistor connected between the zq pin and ground. the single resistor ca n be used for each sdram or one resistor can be shared between two sdrams if the zq calibration timings for each sdram do not overlap. the total capacitive loading on the zq pin must be limited. c k # t 1 t a 0 t a 1 t a 2 t a 3 t 0 c k c k e n o p z q c l n o p v a l i d t z q i n i t o r t z q o p e r d o n ' t c a r e t i m e b r e a k v a l i d t b 0 t b 1 z q c s n o p t z q c s t c 0 t c 1 n o p n o p a d d r e s s n o t e s : 1 . c k e m u s t b e c o n t i n u o u s l y r e g i s t e r e d h i g h d u r i n g t h e c a l i b r a t i o n p r o c e d u r e . 2 . o n - d i e t e r m i n a t i o n m u s t b e d i s a b l e d v i a t h e o d t s i g n a l o r m r s d u r i n g t h e c a l i b r a t i o n p r o c e d u r e . 3 . a l l d e v i c e s c o n n e c t e d t o t h e d q b u s s h o u l d b e h i g h i m p e d a n c e d u r i n g t h e c a l i b r a t i o n p r o c e d u r e . t c 2 n o p v a l i d v a l i d v a l i d v a l i d a 1 0 v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d n o t e s 1 o d t v a l i d v a l i d v a l i d n o t e s 2 h i - z a c t i v i t i e s h i - z n o t e s 3 c o m m a n d d q b u s a c t i v i t i e s n o t e s 1 n o t e s 2 n o t e s 3
1gb ddr3l C as4c128m8d3l confidential 57 rev. 2 . 0 a ug . / 20 1 4 - single - ended requirements for differential signals each individual component of a differential signal (ck, ck# , dqs, dqs# ) has also to comply with certain requirements for single - ended signals. ck and ck# have to approximately reach vsehmin / vselmax (approximately equal to the ac - levels (vih(ac) / vil(ac)) for add/cmd signals ) in every half - cycle. dqs , dqs# have to reach vsehmin / vselmax (approximately the ac - levels (vih(ac) / vil(ac)) for dq signals) in every half - cycle proceeding and following a valid transition. note that the applicable ac - levels for add/c md and dqs might be different per speed - bin etc. e.g., if vih150(ac)/vil150(ac) is used for add/cmd signals, then these ac - levels apply also for the single - ended signals ck and ck# . table 2 9 . single - ended levels for ck, dqs, ck#, dqs# symbol parameter min. max. unit note vseh single - ended high level for strobes ( v dd / 2) + 0.175 - v 1 ~3 single - ended high level for ck, ck# ( v dd / 2) + 0.175 - v 1~3 vsel single - ended low level for strobes - ( v dd / 2) - 0.175 v 1~3 single - ended low level for ck, ck# - ( v dd / 2) - 0.175 v 1~3 note 1 : for ck, ck# use vih/vil(ac) of add/cmd; for strobes (dqs, dqs#) use vih/vil(ac) of dqs. note 2 : vih(ac)/vil(ac) for dqs is based on vrefdq; vih(ac)/vil(ac) for add/cmd is based on vrefca; if a reduced ac - high or ac - low le vel is used for a signal group, then the reduced level applies also here . note 3 : these values are not defined, however the single - ended signals ck, ck#, dqs, dqs# need to be within the respective limits (vih(dc) max, vil(dc)min) for single - ended signals a s well as the limitations for overshoot and undershoot. - differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input s ignals (ck, ck # and dqs, dqs # ) must meet the requirements in the following table. the differential input cross point voltage vix is measured from the actual cross point of true and complete signal to the midlevel between of vdd and vss. table 30 . cross p oint voltage for differential input signals (ck, dqs) symbol parameter min. max. unit note vix(ck) differential input cross point voltage relative to vdd/2 for ck, ck# - 150 150 mv 2 vix(dqs) differential input cross point voltage relative to vdd/2 for d qs, dqs# - 150 150 m v 2 note 1 : extended range for vix is only allowed for clock and if single - ended clock input signals ck and ck# is monotonic with a single - ended swing vsel / vseh of at least vdd/2 +/ - 250 mv, and when the differential slew rate of ck - ck# is larger than 3 v/ns. note 2 : the relation between vix min/max and vsel/vseh should satisfy following. (vdd/2) + vix (min) - vsel R 25mv vseh - ((vdd/2) + vix (max)) R 25mv
1gb ddr3l C as4c128m8d3l confidential 58 rev. 2 . 0 a ug . / 20 1 4 - slew rate definition for differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are defined and measured as shown below. table 3 1 . differential input slew rate definition description measured defined by from to differential input slew rate for rising edge (ck , ck# and dqs , dqs# ) vildif fmax vihdiffmin [vihdiffmin - vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck , ck# and dqs , dqs# ) vihdiffmin vildiffmax [vihdiffmin - vildiffmax] / deltatfdiff note: the differential signal (i.e., ck , ck# and dqs , dqs#) must be li near between these thresholds. table 3 2 . single - ended ac and dc output levels symbol parameter - 12 unit note v oh (dc) dc output high measurement level (for iv curve linearity) 0.8 x v dd q v v om (dc) dc output mid measurement level (for iv curve linearity ) 0.5 x v dd q v v ol (dc) dc output low measurement level (for iv curve linearity) 0.2 x v dd q v v oh (ac) ac output high measurement level (for output sr) v tt + 0.1 x v dd q v 1 v ol (ac) ac output low measurement level (for output sr) v tt - 0.1 x v dd q v 1 no te 1: the swing of 0.1 vddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to vtt = vddq/2. table 3 3 . differential ac and dc output levels symbol pa rameter - 12 unit note v ohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x v dd q v 1 v oldiff (ac) ac differential output low measurement level (for output sr) - 0.2 x v dd q v 1 note 1 : the swing of 0.2 vddq is based on ap proximately 50% of the static single - ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to vtt = vddq/2 at each of the differential outputs.
1gb ddr3l C as4c128m8d3l confidential 59 rev. 2 . 0 a ug . / 20 1 4 - single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol( ac) and voh(ac) for single ended signals as shown in table . table 3 4 . output slew rate definition ( single - ended ) description measured defined by from to single - ended output slew rate for rising edge vol(ac) voh(ac) [voh(ac) - vol(ac)] / deltatrse si ngle - ended output slew rate for fall ing edge voh(ac) vol(ac) [voh(ac) - vol(ac)] / deltat f se note: output slew rate is verified by design and characterization, and may not be subject to production test. table 3 5 . output slew rate (single - ended) symbol parameter - 12 unit min. max. srqse single - ended output slew rate 1.75 5 v/ns description: sr: slew rate q: query output (like in dq, which stands for data - in, query - output) se: single - ended signals for ron = rzq/7 setting - differential output sle w rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between voldiff(ac) and vohdiff(ac) for differential signals as shown in table. table 3 6 . output slew rate definition ( different ial ) description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) [vohdiff(ac) - voldiff(ac)] / deltatrdiff differential output slew rate for fall ing edge vohdiff(ac) voldiff(ac) [vohdiff(ac) - voldiff( ac)] / deltat f diff note: output slew rate is verified by design and characterization, and may not be subject to production test . table 3 7 . output slew rate ( differential ) symbol parameter - 12 unit min. max. srq diff differential output slew rate 3.5 12 v/ns description: sr: slew rate q: query output (like in dq, which stands for data - in, query - output) diff: differential signals for ron = rzq/7 setting
1gb ddr3l C as4c128m8d3l confidential 60 rev. 2 . 0 a ug . / 20 1 4 ? reference load for ac timing and output slew rate the following figure represents the effectiv e reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of any particular system environment or a depiction of the actual load pre sented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transmissio n lines terminated at the tester electronics. figure 24 . reference load for ac timing and output slew rate table 3 8 . ac overshoot/undershoot specification for address and control pins parameter - 12 unit maximum peak ampli tude allowed for overshoot area. 0.4 v maximum peak amplitude allowed for undershoot area. 0.4 v maximum overshoot area above vdd 0.33 v - ns maximum undershoot area below vss 0.33 v - ns table 3 9 . ac overshoot/undershoot specification for clock, dat a, strobe and mask parameter - 12 unit maximum peak amplitude allowed for overshoot area. 0.4 v maximum peak amplitude allowed for undershoot area. 0.4 v maximum overshoot area above vdd 0.13 v - ns maximum undershoot area below vss 0.13 v - ns d u t d q d q s d q s # v d d q c k , c k # 2 5 o h m v t t = v d d q / 2
1gb ddr3l C as4c128m8d3l confidential 61 rev. 2 . 0 a ug . / 20 1 4 - addre ss / command setup, hold and derating for all input signals the total tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis(base) and tih(base) and tih(base) value to the delta tis and delta tih derating value respectivel y. example: tis (total setup time) = tis(base) + delta tis . setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tis) nominal slew rate for a fallin g signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate for derati ng value. if the actual signal is later than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value. hold (tih) nominal sle w rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded dc to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere bet ween shaded dc to vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value. for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac. altho ugh for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). table 40 . add/cmd setup and hold base - values for 1v/ns symbol reference - 12 unit t is (base) ac1 60 v ih/l (ac) 65 ps t is (base) ac1 35 v ih/l (ac) 185 ps t ih (base) dc 9 0 v ih/l (dc) 13 0 ps note 1 : (ac/dc referenced for 1v/ns address/command slew rate and 2 v/ns differential ck - ck# slew rate) note 2 : the tis(base) ac 135 specifications are adjusted from the tis(base) specification by adding an additional 100ps of derating to accommodate for the lower alternate threshold of 1 35 mv and another 25 ps to account for the earlier reference point [(1 60 mv - 1 35 mv) / 1 v/ns]. table 4 1 . derating values ddr 3 l - 1600 t i s/t i h C ( ac1 60) t i s , t i h derating in [ps] ac/dc based ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v /ns t i s t i h t i s t i h t i s t i h t i s t i h t i s t i h t i s t i h t i s t i h t i s t i h cmd /add slew rate v/ns 2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95 1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 - 1 - 3 - 1 - 3 - 1 - 3 7 5 15 13 23 21 31 31 39 47 0.8 - 3 - 8 - 3 - 8 - 3 - 8 5 1 13 9 21 17 29 27 37 43 0.7 - 5 - 13 - 5 - 13 - 5 - 13 3 - 5 11 3 19 11 27 21 35 37 0.6 - 8 - 20 - 8 - 20 - 8 - 20 0 - 12 8 - 4 16 4 24 14 32 30 0.5 - 20 - 30 - 20 - 30 - 20 - 30 - 12 - 22 - 4 - 14 4 - 6 12 4 20 20 0.4 - 40 - 45 - 40 - 45 - 40 - 45 - 32 - 37 - 24 - 29 - 16 - 21 - 8 - 11 0 5
1gb ddr3l C as4c128m8d3l confidential 62 rev. 2 . 0 a ug . / 20 1 4 table 4 2 . derating values ddr 3 l - 1600 t i s/t i h C ( ac1 35) t i s , t i h derating in [ps] ac/dc based ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t i s t i h t i s t i h t i s t i h t i s t i h t i s t i h t i s t i h t i s t i h t i s t i h cmd /add slew rate v/ns 2.0 68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 95 1.5 45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 - 3 2 - 3 2 - 3 10 5 18 13 26 21 34 31 42 47 0.8 3 - 8 3 - 8 3 - 8 11 1 19 9 27 17 35 27 43 43 0.7 6 - 13 6 - 13 6 - 13 14 - 5 22 3 30 11 38 21 46 37 0.6 9 - 20 9 - 20 9 - 20 17 - 12 25 - 4 33 4 41 14 49 30 0.5 5 - 30 5 - 30 5 - 30 13 - 22 21 - 14 29 - 6 37 4 45 20 0.4 - 3 - 45 - 3 - 45 - 3 - 45 6 - 37 14 - 29 22 - 21 30 - 11 38 5
1gb ddr3l C as4c128m8d3l confidential 63 rev. 2 . 0 a ug . / 20 1 4 - data setup, hold, and slew rate de - rat ing for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base) and tdh(base) value to the tds and tdh derating value respectively. example: tds (total setup time) = tds(base) + tds. se tup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded vref(dc) to ac region, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded vref(dc) to ac region, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value. hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always la ter than the nominal slew rate line between shaded dc level to vref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value. for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac. although for slow slew rates the total setup time might be ne gative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in the follow ing tables, the derating values may be obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterizatio n. table 4 3 . data setup and hold base - values symbol reference - 12 unit t d s (base) ac1 35 v ih/l (ac) 25 ps t dh (base) dc 9 0 v ih/l ( d c) 55 ps note 1 : (ac/dc referenced for 1v/ns address/command slew rate and 2 v/ns differential ck - ck# slew rate) table 4 4 . derating values for ddr 3 l - 1600 t d s/t d h C (ac1 35 ) t d s , t d h derating in [ps] ac/dc based dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h dq slew rate v/ns 2.0 68 45 68 45 68 45 - - - - - - - - - - 1.5 45 30 45 30 45 30 53 38 - - - - - - - - 1.0 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 2 - 3 2 - 3 10 5 18 13 26 21 - - - - 0.8 - - - - 3 - 8 11 1 1 9 9 2 7 17 35 27 - - 0.7 - - - - - - 14 - 5 22 3 30 11 38 21 4 6 37 0.6 - - - - - - - - 25 - 4 33 4 41 14 49 30 0.5 - - - - - - - - - - 29 - 6 37 4 45 20 0.4 - - - - - - - - - - - - 30 - 11 38 5
1gb ddr3l C as4c128m8d3l confidential 64 rev. 2 . 0 a ug . / 20 1 4 timing waveforms figure 2 5 . mpr readout of predefined pattern,bl8 fixed burst order, single readout figure 2 6 . mpr rea dout of predefined pattern,bl8 fixed burst order, back to back readout d o n ' t c a r e t i m e b r e a k m r s p r e a r e a d n o p n o p n o p n o p n o p n o p n o p n o p m r s t r p n o t e s : 1 . r d w i t h b l 8 e i t h e r b y m r s o r o t f . 2 . m e m o r y c o n t r o l l e r m u s t d r i v e 0 o n a [ 2 : 0 ] . t 0 t a t b 0 t b 1 t c 0 t c 1 t c 2 t c 3 t c 4 t c 5 t c 6 t c 7 c k # c k b a a [ 1 : 0 ] a [ 2 ] a [ 1 1 ] a 1 2 , b c # a [ 9 : 3 ] a 1 0 , a p t c 8 t c 9 t d m r s m r s v a l i d t m o d n o t e s 1 t m p r r t m o d 3 v a l i d 3 0 0 v a l i d 1 0 0 0 0 v a l i d 0 0 0 v a l i d 0 0 v a l i d 0 0 v a l i d 0 0 v a l i d 0 a [ 1 4 : 1 3 ] d q 1 r l n o t e s 2 n o t e s 2 d q s , d q s # c o m m a n d d o n ' t c a r e t i m e b r e a k m r s p r e a r e a d r e a d n o p n o p n o p n o p n o p n o p n o p n o p t r p n o t e s : 1 . r d w i t h b l 8 e i t h e r b y m r s o r o t f . 2 . m e m o r y c o n t r o l l e r m u s t d r i v e 0 o n a [ 2 : 0 ] . t 0 t a t b t c 0 t c 1 t c 2 t c 3 t c 4 t c 5 t c 6 t c 7 t c 8 c k # c k b a a [ 1 : 0 ] a [ 2 ] a [ 1 1 ] a 1 2 , b c # a [ 9 : 3 ] a 1 0 , a p t c 9 t c 1 0 t d n o p m r s v a l i d t m o d n o t e s 1 t m p r r t m o d 3 v a l i d 3 0 0 v a l i d 1 0 0 0 0 v a l i d 0 0 0 v a l i d 0 0 v a l i d 0 0 v a l i d 0 0 v a l i d 0 a [ 1 4 : 1 3 ] d q 1 r l n o t e s 2 n o t e s 2 n o t e s 1 t c c d v a l i d 0 0 v a l i d v a l i d v a l i d v a l i d v a l i d n o t e s 2 n o t e s 1 n o t e s 1 n o t e s 2 d q s , d q s # c o m m a n d r l
1gb ddr3l C as4c128m8d3l confidential 65 rev. 2 . 0 a ug . / 20 1 4 figure 2 7 . mpr readout of predefined pattern,bc4 lower nibble then upper nibble figure 2 8 . mpr readout of predefined pat tern,bc4 upper nibble then lower nibble d o n ' t c a r e t i m e b r e a k m r s p r e a r e a d r e a d n o p n o p n o p n o p n o p n o p n o p m r s t r p n o t e s : 1 . r d w i t h b c 4 e i t h e r b y m r s o r o t f . 2 . m e m o r y c o n t r o l l e r m u s t d r i v e 0 o n a [ 1 : 0 ] . 3 . a [ 2 ] = 0 s e l e c t s l o w e r 4 n i b b l e b i t s 0 . . . . 3 . 4 . a [ 2 ] = 1 s e l e c t s u p p e r 4 n i b b l e b i t s 4 . . . . 7 . t 0 t a t b t c 0 t c 1 t c 2 t c 3 t c 4 t c 5 t c 6 t c 7 t c 8 c k # c k b a a [ 1 : 0 ] a [ 2 ] a [ 1 1 ] a 1 2 , b c # a [ 9 : 3 ] a 1 0 , a p t c 9 t c 1 0 t d n o p n o p v a l i d t m o d n o t e s 1 t m p r r t m o d 3 v a l i d 3 0 0 v a l i d 1 0 0 0 0 v a l i d 0 0 0 v a l i d 0 0 v a l i d 0 0 v a l i d 0 0 v a l i d 0 a [ 1 4 : 1 3 ] d q 1 r l n o t e s 2 n o t e s 3 n o t e s 1 t c c d v a l i d 0 1 v a l i d v a l i d v a l i d v a l i d v a l i d n o t e s 2 n o t e s 1 n o t e s 1 n o t e s 4 d q s , d q s # c o m m a n d r l d o n ' t c a r e t i m e b r e a k m r s p r e a r e a d r e a d n o p n o p n o p n o p n o p n o p n o p m r s t r p n o t e s : 1 . r d w i t h b c 4 e i t h e r b y m r s o r o t f . 2 . m e m o r y c o n t r o l l e r m u s t d r i v e 0 o n a [ 1 : 0 ] . 3 . a [ 2 ] = 0 s e l e c t s l o w e r 4 n i b b l e b i t s 0 . . . . 3 . 4 . a [ 2 ] = 1 s e l e c t s u p p e r 4 n i b b l e b i t s 4 . . . . 7 . t 0 t a t b t c 0 t c 1 t c 2 t c 3 t c 4 t c 5 t c 6 t c 7 t c 8 c k # c k b a a [ 1 : 0 ] a [ 2 ] a [ 1 1 ] a 1 2 , b c # a [ 9 : 3 ] a 1 0 , a p t c 9 t c 1 0 t d n o p n o p v a l i d t m o d n o t e s 1 t m p r r t m o d 3 v a l i d 3 0 0 v a l i d 1 1 0 0 0 v a l i d 0 0 0 v a l i d 0 0 v a l i d 0 0 v a l i d 0 0 v a l i d 0 a [ 1 4 : 1 3 ] d q 1 r l n o t e s 2 n o t e s 4 n o t e s 1 t c c d v a l i d 0 0 v a l i d v a l i d v a l i d v a l i d v a l i d n o t e s 2 n o t e s 1 n o t e s 1 n o t e s 3 d q s , d q s # c o m m a n d r l
1gb ddr3l C as4c128m8d3l confidential 66 rev. 2 . 0 a ug . / 20 1 4 figure 29 . read (bl8) to read (bl8) figure 3 0 . nonconsecutive read (bl8) to read (bl8) figure 3 1 . read (bl4) to read ( bl4) n o p r e a d n o p n o p r e a d n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b l 8 , r l = 5 ( c l = 5 , a l = 0 ) 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d s a t t 0 a n d t 4 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p t c c d n o t e s 3 n o t e s 4 b a n k , c o l n b a n k , c o l b d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b + 6 d o u t b + 7 t r p s t t r p r e r l = 5 r l = 5 d o n ' t c a r e t r a n s i t i o n i n g d a t a n o t e s 2 d q s , d q s # a d d r e s s c o m m a n d n o p r e a d n o p n o p n o p r e a d n o p n o p n o p n o p n o p n o p n o t e s : 1 . b l 8 , r l = 5 ( c l = 5 , a l = 0 ) , t c c d = 5 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d s a t t 0 a n d t 4 5 . d q s - d q s # i s h e l d l o g i c l o w a t t 9 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p t c c d = 5 n o t e s 3 n o t e s 4 b a n k , c o l n b a n k , c o l b d o n d o b t r p s t t r p r e r l = 5 r l = 5 d o n ' t c a r e t r a n s i t i o n i n g d a t a n o t e s 2 d q s , d q s # a d d r e s s c o m m a n d n o t e s 5 n o p r e a d n o p n o p r e a d n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b c 4 , r l = 5 ( c l = 5 , a l = 0 ) 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 1 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d s a t t 0 a n d t 4 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p t c c d n o t e s 3 n o t e s 4 b a n k , c o l n b a n k , c o l b d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 t r p r e r l = 5 r l = 5 d o n ' t c a r e t r a n s i t i o n i n g d a t a n o t e s 2 d q s , d q s # a d d r e s s c o m m a n d t r p s t t r p s t t r p r e
1gb ddr3l C as4c128m8d3l confidential 67 rev. 2 . 0 a ug . / 20 1 4 figure 3 2 . read (bl8) to write (bl8) figure 3 3 . read (bl4) to write (bl4) otf figure 3 4 . read (bl8) to read (bl4) otf n o p r e a d n o p n o p n o p r e a d n o p n o p n o p n o p n o p n o p n o t e s : 1 . b l 8 , r l = 5 ( c l = 5 , a l = 0 ) , t c c d = 5 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d s a t t 0 a n d t 4 5 . d q s - d q s # i s h e l d l o g i c l o w a t t 9 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p t c c d = 5 n o t e s 3 n o t e s 4 b a n k , c o l n b a n k , c o l b d o n d o b t r p s t t r p r e r l = 5 r l = 5 d o n ' t c a r e t r a n s i t i o n i n g d a t a n o t e s 2 d q s , d q s # a d d r e s s c o m m a n d n o t e s 5 n o p r e a d n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b c 4 , r l = 5 ( c l = 5 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n , d i n b = d a t a - i n f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d a t t 0 a n d w r i t e c o m m a n d a t t 4 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d / 2 + 2 t c k - w l n o t e s 3 n o t e s 4 b a n k , c o l n b a n k , c o l b d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d i n b d i n b + 1 d i n b + 2 d i n b + 3 t r p r e r l = 5 w l = 5 d o n ' t c a r e t r a n s i t i o n i n g d a t a n o t e s 2 d q s , d q s # a d d r e s s c o m m a n d t r p s t t w p r e t 1 5 n o p t w p s t 4 c l o c k s t w r t w t r n o p r e a d n o p n o p r e a d n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . r l = 5 ( c l = 5 , a l = 0 ) 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 0 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d a t t 4 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p t c c d n o t e s 3 n o t e s 4 b a n k , c o l n b a n k , c o l b d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 t r p r e r l = 5 r l = 5 d o n ' t c a r e t r a n s i t i o n i n g d a t a n o t e s 2 d q s , d q s # a d d r e s s c o m m a n d t r p s t d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7
1gb ddr3l C as4c128m8d3l confidential 68 rev. 2 . 0 a ug . / 20 1 4 figure 3 5 . read (bl4) to read (bl8) otf figure 36 . r ead (bc4) to write (bl8) otf figure 37 . read (bl8) to write (bl4) otf n o p r e a d n o p n o p r e a d n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . r l = 5 ( c l = 5 , a l = 0 ) 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d a t t 0 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 4 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p t c c d n o t e s 3 n o t e s 4 b a n k , c o l n b a n k , c o l b d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t b + 4 d o u t b + 5 d o u t b + 6 d o u t b + 7 t r p r e r l = 5 r l = 5 d o n ' t c a r e t r a n s i t i o n i n g d a t a n o t e s 2 d q s , d q s # a d d r e s s c o m m a n d t r p s t d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 t r p s t t r p r e n o p r e a d n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b c 4 , r l = 5 ( c l = 5 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n , d i n b = d a t a - i n f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d a t t 0 a n d w r i t e c o m m a n d a t t 4 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d / 2 + 2 t c k - w l n o t e s 3 n o t e s 4 b a n k , c o l n b a n k , c o l b d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d i n b d i n b + 1 d i n b + 2 d i n b + 3 t r p r e r l = 5 w l = 5 d o n ' t c a r e t r a n s i t i o n i n g d a t a n o t e s 2 d q s , d q s # a d d r e s s c o m m a n d t r p s t t w p r e t 1 5 n o p t w p s t 4 c l o c k s t w r t w t r d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 n o p r e a d n o p n o p n o p n o p w r i t e n o p n o p n o p n o p n o p n o t e s : 1 . r l = 5 ( c l = 5 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n , d i n b = d a t a - i n f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 0 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 6 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d + 2 t c k - w l n o t e s 3 n o t e s 4 b a n k , c o l n b a n k , c o l b d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d i n b d i n b + 1 d i n b + 2 d i n b + 3 t r p r e r l = 5 w l = 5 d o n ' t c a r e t r a n s i t i o n i n g d a t a n o t e s 2 d q s , d q s # a d d r e s s c o m m a n d t r p s t t w p r e t 1 5 n o p t w p s t d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 4 c l o c k s t w r t w t r
1gb ddr3l C as4c128m8d3l confidential 69 rev. 2 . 0 a ug . / 20 1 4 figure 38 . read to precharge, rl = 5, al = 0, cl = 5, trtp = 4, trp = 5 figure 3 9 . read to precharge, rl = 8, al = cl - 2, cl = 5, trtp = 6, trp = 5 r e a d n o p n o p n o p n o p p r e n o p n o p n o p n o p a c t n o p n o t e s : 1 . r l = 5 ( c l = 5 , a l = 0 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . t h e e x a m p l e a s s u m e s t r a s . m i n i s s a t i s f i e d a t p r e c h a r g e c o m m a n d t i m e ( t 5 ) a n d t h a t t r c . m i n i s s a t i s f i e d a t t h e n e x t a c t i v e c o m m a n d t i m e ( t 1 0 ) . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p r l = a l + c l b a n k a , ( o r a l l ) b a n k a , r o w b d o n d o n + 1 d o n + 2 d o n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a t 1 5 n o p t r p t r t p b a n k a , c o l n d q d o n d o n + 1 d o n + 2 d o n + 3 b l 4 o p e r a t i o n : b l 8 o p e r a t i o n : d o n + 4 d o n + 5 d o n + 6 d o n + 7 d q s , d q s # d q s , d q s # a d d r e s s c o m m a n d r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p p r e n o p n o t e s : 1 . r l = 8 ( c l = 5 , a l = c l - 2 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . t h e e x a m p l e a s s u m e s t r a s . m i n i s s a t i s f i e d a t p r e c h a r g e c o m m a n d t i m e ( t 1 0 ) a n d t h a t t r c . m i n i s s a t i s f i e d a t t h e n e x t a c t i v e c o m m a n d t i m e ( t 1 5 ) . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p a l = c l - 2 = 3 b a n k a , ( o r a l l ) d o n d o n + 1 d o n + 2 d o n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a t 1 5 a c t t r t p b a n k a , c o l n d q d o n d o n + 1 d o n + 2 d o n + 3 b l 4 o p e r a t i o n : b l 8 o p e r a t i o n : d o n + 4 d o n + 5 d o n + 6 d o n + 7 b a n k a , r o w b c l = 5 t r p d q s , d q s # d q s , d q s # a d d r e s s c o m m a n d
1gb ddr3l C as4c128m8d3l confidential 70 rev. 2 . 0 a ug . / 20 1 4 figure 4 0 . write timing definition and parameters n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b l 8 , w l = 5 ( a l = 0 , c w l = 5 ) 2 . d i n n = d a t a - i n f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 0 . 5 . t d q s s m u s t b e m e t a t e a c h r i s i n g c l o c k e d g e . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k d q w l = a l + c w l d i n n d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k c o l n d m n o t e s 3 n o t e s 4 n o t e s 2 t d q s s ( m i n ) t w p r e ( m i n ) t d q s h ( m i n ) t d q s l t d q s s t d s h t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l ( m i n ) t d s h t d s h t w p s t ( m i n ) t d s s t d s s t d s s t d s s t d s s d i n n + 4 d i n n + 6 d i n n + 7 d q d i n n d i n n + 2 d i n n + 3 d m n o t e s 2 t d q s s ( n o m i n a l ) t w p r e ( m i n ) t d q s h ( m i n ) t d q s l t d s h t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l ( m i n ) t d s h t d s h t d s h t w p s t ( m i n ) t d s s t d s s t d s s t d s s t d s s d i n n + 4 d i n n + 6 d i n n + 7 t d s h d q d i n n d i n n + 2 d i n n + 3 d m n o t e s 2 t d q s s ( m a x ) t w p r e ( m i n ) t d q s h ( m i n ) t d q s l t d s h t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l ( m i n ) t d s h t d s h t d s h t w p s t ( m i n ) t d s s t d s s t d s s t d s s t d s s d i n n + 4 d i n n + 6 d i n n + 7 t d q s s c o m m a n d a d d r e s s d q s , d q s # d q s , d q s # d q s , d q s #
1gb ddr3l C as4c128m8d3l confidential 71 rev. 2 . 0 a ug . / 20 1 4 figure 4 1 . write burst operation wl = 5 (al = 0, cwl = 5, bl8) figure 4 2 . write burst operation wl = 9 (al = cl - 1, cwl = 5, bl8) n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b l 8 , w l = 5 ; a l = 0 , c w l = 5 . 2 . d i n n = d a t a - i n f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 0 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k d q w l = a l + c w l d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a t w p r e b a n k , c o l n n o t e s 2 d i n n + 4 d i n n + 5 d i n n + 6 d i n n + 7 d q s , d q s # c o m m a n d a d d r e s s n o t e s 3 n o t e s 4 t w p s t n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b l 8 , w l = 9 ; a l = ( c l - 1 ) , c l = 5 , c w l = 5 . 2 . d i n n = d a t a - i n f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 0 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k d q a l = 4 d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a t w p r e b a n k , c o l n n o t e s 2 n o t e s 3 n o t e s 4 d q s , d q s # a d d r e s s c o m m a n d c w l = 5 w l = a l + c w l
1gb ddr3l C as4c128m8d3l confidential 72 rev. 2 . 0 a ug . / 20 1 4 figure 4 3 . write(bc 4) to read (bc4) operation , figure 44 . write(bc4) to precharge operation n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p r e a d n o t e s : 1 . b c 4 , w l = 5 , r l = 5 . 2 . d i n n = d a t a - i n f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 1 0 ] d u r i n g w r i t e c o m m a n d a t t 0 a n d r e a d c o m m a n d a t t n . 5 . t w t r c o n t r o l s t h e w r i t e t o r e a d d e l a y t o t h e s a m e d e v i c e a n d s t a r t s w i t h t h e f i r s t r i s i n g c l o c k e d g e a f t e r t h e l a s t w r i t e d a t a s h o w n a t t 7 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t n c k # c k d q d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k , c o l n n o t e s 2 d q s , d q s # c o m m a n d a d d r e s s n o t e s 3 n o t e s 4 t w p s t t w t r w l = 5 r l = 5 t i m e b r e a k n o t e s 5 t w p r e n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p p r e n o t e s : 1 . b c 4 , w l = 5 , r l = 5 . 2 . d i n n = d a t a - i n f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 1 0 ] d u r i n g w r i t e c o m m a n d a t t 0 . 5 . t h e w r i t e r e c o v e r y t i m e ( t w r ) r e f e r e n c e d f r o m t h e f i r s t r i s i n g c l o c k e d g e a f t e r t h e l a s t w r i t e d a t a s h o w n a t t 7 . t w r s p e c i f i e s t h e l a s t b u r s t w r i t e c y c l e u n t i l t h e p r e c h a r g e c o m m a n d c a n b e i s s u e d t o t h e s a m e b a n k . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t n c k # c k d q d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a t w p r e b a n k , c o l n n o t e s 2 d q s , d q s # c o m m a n d a d d r e s s n o t e s 3 n o t e s 4 t w p s t t w r w l = 5 t i m e b r e a k n o t e s 5
1gb ddr3l C as4c128m8d3l confidential 73 rev. 2 . 0 a ug . / 20 1 4 figure 4 5. write(bc4) otf to precharge operation n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b c 4 o t f , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 o t f s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 0 . 5 . t h e w r i t e r e c o v e r y t i m e ( t w r ) s t a r t s a t t h e r i s i n g c l o c k e d g e t 9 ( 4 c l o c k s f r o m t 5 ) . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t a 0 t a 1 t a 2 p r e n o p n o p d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k c o l n v a l i d 4 c l o c k s t w r n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d d q s , d q s # t w p r e t w p s t t i m e b r e a k w l = 5 n o t e s 5
1gb ddr3l C as4c128m8d3l confidential 74 rev. 2 . 0 a ug . / 20 1 4 figure 46 . write(bc8) to writ e (bc8) figure 47 . write(bc4) to write(bc4) otf figure 48 . write(bc8) to read(bc4,bc8) otf n o p w r i t e n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b l 8 , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 0 a n d t 4 . 5 . t h e w r i t e r e c o v e r y t i m e ( t w r ) a n d w r i t e t i m i n g p a r a m e t e r ( t w t r ) a r e r e f e r e n c e d f r o m t h e f i r s t r i s i n g c l o c k e d g e a f t e r t h e l a s t w r i t e d a t a s h o w n a t t 1 3 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k c o l n b a n k c o l b 4 c l o c k s n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d d q s , d q s # t w p r e t w p s t t c c d d i n n + 4 d i n n + 5 d i n n + 6 d i n n + 7 d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 t w r t w t r w l = 5 w l = 5 n o p w r i t e n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . b c 4 , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 0 a n d t 4 . 5 . t h e w r i t e r e c o v e r y t i m e ( t w r ) a n d w r i t e t i m i n g p a r a m e t e r ( t w t r ) a r e r e f e r e n c e d f r o m t h e f i r s t r i s i n g c l o c k e d g e a t t 1 3 ( 4 c l o c k s f r o m t 9 ) . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k c o l n b a n k c o l b 4 c l o c k s n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d d q s , d q s # t w p r e t w p s t t c c d d i n b d i n b + 1 d i n b + 2 d i n b + 3 t w r t w t r w l = 5 w l = 5 t w p s t t w p r e n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . r l = 5 ( c l = 5 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n = d a t a - i n f r o m c o l u m n n ; d o u t b = d a t a - o u t f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 [ a 1 : 0 = 0 0 ] o r m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 0 . r e a d c o m m a n d a t t 1 3 c a n b e e i t h e r b c 4 o r b l 8 d e p e n d i n g o n m r 0 [ a 1 : 0 ] a n d a 1 2 s t a t u s a t t 1 3 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p r e a d n o p d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k c o l n b a n k c o l b n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d d q s , d q s # t w p r e d i n n + 4 d i n n + 5 d i n n + 6 d i n n + 7 r l = 5 t w t r w l = 5 t w p s t
1gb ddr3l C as4c128m8d3l confidential 75 rev. 2 . 0 a ug . / 20 1 4 figure 49 . write(bc4) to read(bc4,bc8) otf figure 5 0 . write(bc4) to read(bc4) figure 5 1 . write(bc8) to write(bc4) o tf n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . r l = 5 ( c l = 5 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n = d a t a - i n f r o m c o l u m n n ; d o u t b = d a t a - o u t f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 0 . r e a d c o m m a n d a t t 1 3 c a n b e e i t h e r b c 4 o r b l 8 d e p e n d i n g o n a 1 2 s t a t u s a t t 1 3 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p r e a d n o p d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k c o l n b a n k c o l b n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d d q s , d q s # t w p r e r l = 5 t w t r w l = 5 t w p s t 4 c l o c k s n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p r e a d n o t e s : 1 . r l = 5 ( c l = 5 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n = d a t a - i n f r o m c o l u m n n ; d o u t b = d a t a - o u t f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 1 0 ] . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k c o l n b a n k c o l b n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d d q s , d q s # t w p r e r l = 5 t w t r w l = 5 t w p s t n o p w r i t e n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 0 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 4 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k c o l n b a n k c o l b n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d d q s , d q s # t w p r e d i n n + 4 d i n n + 5 d i n n + 6 d i n n + 7 t w t r w l = 5 t w p s t t c c d t w r 4 c l o c k s w l = 5 d i n b d i n b + 1 d i n b + 2 d i n b + 3
1gb ddr3l C as4c128m8d3l confidential 76 rev. 2 . 0 a ug . / 20 1 4 figure 5 2 . write(bc4) to write(bc8) otf figure 5 3 . refresh command timing figure 54 . self - refresh entry / exit timing n o p w r i t e n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o t e s : 1 . w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 0 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 [ a 1 : 0 = 0 1 ] a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 4 . t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d q t 1 2 t 1 3 t 1 4 n o p n o p n o p d i n n d i n n + 1 d i n n + 2 d i n n + 3 d o n ' t c a r e t r a n s i t i o n i n g d a t a b a n k c o l n b a n k c o l b 4 c l o c k s n o t e s 3 n o t e s 2 a d d r e s s n o t e s 4 c o m m a n d d q s , d q s # t w p r e t w p s t t c c d d i n b d i n b + 1 d i n b + 2 d i n b + 3 t w r t w t r w l = 5 w l = 5 t w p s t t w p r e d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 n o p r e f n o p r e f n o p n o p v a l i d v a l i d v a l i d v a l i d v a l i d r e f n o t e s : 1 . o n l y n o p / d e s c o m m a n d s a l l o w e d a f t e r r e f r e s h c o m m a n d r e g i s t e r e d u n t i l t r f c ( m i n ) e x p i r e s . 2 . t i m e i n t e r v a l b e t w e e n t w o r e f r e s h c o m m a n d s m a y b e e x t e n d e d t o a m a x i m u m o f 9 x t r e f i . t 0 t 1 t a 0 t a 1 t b 0 t b 1 t b 2 t b 3 t c 0 c k # c k t c 1 t c 2 t c 3 v a l i d v a l i d v a l i d d o n ' t c a r e t r a n s i t i o n i n g d a t a t r f c ( m i n ) c o m m a n d t r f c t r e f i ( m a x . 9 * t r e f i ) d r a m m u s t b e i d l e d r a m m u s t b e i d l e t i m e b r e a k c k # t 1 t 2 t a 0 t b 0 t c 0 t c 1 t d 0 t e o t 0 c k t c k s r e t f 0 t c k e s r t x s t x s d l l n o p s r e n o p v a l i d n o p v a l i d v a l i d o d t c k e c o m m a n d a d d r t i s d o n ' t c a r e t i m e b r e a k n o t e s : 1 . o n l y n o p o r d e s c o m m a n d . 2 . v a l i d c o m m a n d s n o t r e q u i r i n g a l o c k e d d l l . 3 . v a l i d c o m m a n d s r e q u i r i n g a l o c k e d d l l . t c k s r x v a l i d t c p d e d t i s v a l i d s r x n o t e s 1 n o t e s 2 v a l i d v a l i d t r p o d t l e n t e r s e l f r e f r e s h e x i t s e l f r e f r e s h n o t e s 3
1gb ddr3l C as4c128m8d3l confidential 77 rev. 2 . 0 a ug . / 20 1 4 figure 55 . active power - down entry and exit timing diagram figure 5 6. power - down entry after read and read with auto precharge c k # t 1 t 2 t a 0 t a 1 t b 0 t b 1 t c 0 t 0 c k c k e n o p v a l i d n o p n o p n o p n o p v a l i d t i s t i h t i s t i h v a l i d v a l i d v a l i d v a l i d t c k e t p d t c p d e d t x p e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e a d d r e s s c o m m a n d d o n ' t c a r e t i m e b r e a k n o t e : v a l i d c o m m a n d a t t 0 i s a c t , n o p , d e s o r p r e w i t h s t i l l o n e b a n k r e m a i n i n g o p e n a f t e r c o m p l e t i o n o f t h e p r e c h a r g e c o m m a n d . n o p r d o r r d a n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 t a 6 t a 7 t a 8 t b 0 c k # c k t b 1 v a l i d d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 t p d t i s r l = a l + c l d o n ' t c a r e t r a n s i t i o n i n g d a t a a d d r e s s c k e t c p d e d v a l i d v a l i d v a l i d c o m m a n d d q s , d q s # d q b l 8 d i n b d i n b + 1 d i n b + 2 d i n b + 3 d q b c 4 t r d p d e n p o w e r - d o w n e n t r y t i m e b r e a k
1gb ddr3l C as4c128m8d3l confidential 78 rev. 2 . 0 a ug . / 20 1 4 figure 57 . power - down entry after write with auto precharge figure 58 . power - down entry after write n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 t a 6 t a 7 t b 0 t b 1 c k # c k t b 2 n o p d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 w r t i s w l = a l + c w l d o n ' t c a r e t r a n s i t i o n i n g d a t a c k e t c p d e d v a l i d b a n k , c o l n v a l i d d q b l 8 d i n b d i n b + 1 d i n b + 2 d i n b + 3 d q b c 4 t w r a p d e n p o w e r - d o w n e n t r y t i m e b r e a k t c 0 t c 1 n o p v a l i d a 1 0 t p d n o t e s : 1 . w r i s p r o g r a m m e d t h r o u g h m r 0 . s t a r t i n t e r n a l p r e c h a r g e d q s , d q s # a d d r e s s c o m m a n d n o t e s 1 n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 t a 6 t a 7 t b 0 t b 1 c k # c k t b 2 n o p d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 t w r t i s w l = a l + c w l d o n ' t c a r e t r a n s i t i o n i n g d a t a c k e t c p d e d v a l i d b a n k , c o l n v a l i d d q b l 8 d i n b d i n b + 1 d i n b + 2 d i n b + 3 d q b c 4 t w r p d e n p o w e r - d o w n e n t r y t i m e b r e a k t c 0 t c 1 n o p v a l i d a 1 0 t p d d q s , d q s # a d d r e s s c o m m a n d
1gb ddr3l C as4c128m8d3l confidential 79 rev. 2 . 0 a ug . / 20 1 4 figure 59 . precharge power - down (fast e xit mode) entry and exit figure 60 . precharge power - down (slow exit mode) entry and exit c k # t 1 t 2 t a 0 t a 1 t b 0 t b 1 t c 0 t 0 c k c k e n o p v a l i d n o p n o p n o p n o p v a l i d t i s t i s t i h v a l i d v a l i d t c k e t c p d e d e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e c o m m a n d d o n ' t c a r e t i m e b r e a k t p d t x p c k # t 1 t 2 t a 0 t a 1 t b 0 t b 1 t c 0 t 0 c k c k e n o p v a l i d n o p n o p n o p n o p v a l i d t i s t i s t i h v a l i d v a l i d t c k e t c p d e d e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e c o m m a n d d o n ' t c a r e t i m e b r e a k t p d t x p t d 0 v a l i d v a l i d t x p d l l
1gb ddr3l C as4c128m8d3l confidential 80 rev. 2 . 0 a ug . / 20 1 4 figure 61 . refresh command to power - down entry figure 62 . active com mand to power - down entry c k # t 1 t 2 t 3 t a 0 t a 1 t 0 c k c k e r e f v a l i d n o p n o p v a l i d t i s t p d v a l i d t c p d e d d o n ' t c a r e t i m e b r e a k t r e f p d e n n o p v a l i d v a l i d v a l i d a d d r e s s c o m m a n d c k # t 1 t 2 t 3 t a 0 t a 1 t 0 c k c k e a c t i v e v a l i d n o p n o p v a l i d t i s t p d v a l i d t c p d e d d o n ' t c a r e t i m e b r e a k t a c t p d e n n o p v a l i d v a l i d v a l i d a d d r e s s c o m m a n d
1gb ddr3l C as4c128m8d3l confidential 81 rev. 2 . 0 a ug . / 20 1 4 figure 63 . precharge, precharge all command to power - down entry figure 64 . mrs command to power - down entry c k # t 1 t 2 t 3 t a 0 t a 1 t 0 c k c k e p r e o r p r e a v a l i d n o p n o p v a l i d t i s t p d v a l i d t c p d e d d o n ' t c a r e t i m e b r e a k t p r e p d e n n o p v a l i d v a l i d v a l i d a d d r e s s c o m m a n d c k # t 1 t a 0 t a 1 t b 0 t b 1 t 0 c k c k e n o p m r s n o p v a l i d t i s t p d v a l i d t c p d e d d o n ' t c a r e t i m e b r e a k t m r s p d e n n o p v a l i d v a l i d a d d r e s s c o m m a n d
1gb ddr3l C as4c128m8d3l confidential 82 rev. 2 . 0 a ug . / 20 1 4 figure 65 . synchronous odt timing example ( al = 3; cwl = 5; odtlon = al + cwl - 2 = 6 ; odtloff = al + cwl - 2 = 6 ) figure 66 . synchronous odt example with bl = 4, wl = 7 figure 67 . dynamic odt behavior with odt being a sserted before and after the write t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k t 1 2 t a o n ( m i n ) o d t h 4 , m i n d o n ' t c a r e t r a n s i t i o n i n g d a t a o d t a l = 3 t 1 3 t 1 4 c k e t 1 5 c w l - 2 o d t l o f f = c w l + a l - 2 o d t l o n = c w l + a l - 2 d r a m _ r t t t a o n ( m a x ) t a o f ( m i n ) t a o f ( m a x ) r t t _ n o m a l = 3 n o p n o p n o p n o p n o p n o p n o p w r s 4 n o p n o p n o p n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k t 1 2 t 1 3 t 1 4 n o p n o p n o p o d t h 4 d o n ' t c a r e t r a n s i t i o n i n g d a t a t 1 5 n o p o d t l o f f = w l - 2 d r a m _ r t t o d t c o m m a n d c k e t 1 6 t 1 7 n o p n o p o d t h 4 m i n o d t h 4 o d t l o n = w l - 2 o d t l o n = w l - 2 o d t l o f f = w l - 2 r t t _ n o m t a o f ( m i n ) t a o n ( m a x ) t a o f ( m a x ) t a o n ( m i n ) t a o n ( m a x ) t a o n ( m i n ) t a o f ( m i n ) t a o f ( m a x ) n o p n o p n o p n o p w r s 4 n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k t 1 2 t 1 3 t 1 4 n o p n o p n o p d o n ' t c a r e t r a n s i t i o n i n g d a t a t 1 5 n o p o d t t 1 6 t 1 7 n o p n o p o d t h 4 o d t l o n v a l i d r t t d i n n d i n n + 1 d i n n + 2 d i n n + 3 d q o d t l o f f t a d c ( m i n ) t a d c ( m a x ) t a o n ( m i n ) o d t h 4 o d t l c w n 4 t a o n ( m a x ) r t t _ n o m r t t _ w r t a d c ( m i n ) t a d c ( m a x ) t a o f ( m i n ) t a o f ( m a x ) r t t _ n o m o d t l c n w w l n o t e s : e x a m p l e f o r b c 4 ( v i a m r s o r o t f ) , a l = 0 , c w l = 5 . o d t h 4 a p p l i e s t o f i r s t r e g i s t e r i n g o d t h i g h a n d t o t h e r e g i s t r a t i o n o f t h e w r i t e c o m m a n d . i n t h i s e x a m p l e , o d t h 4 w o u l d b e s a t i s f i e d i f o d t w e n t l o w a t t 8 ( 4 c l o c k s a f t e r t h e w r i t e c o m m a n d ) . d q s , d q s # c o m m a n d a d d r e s s
1gb ddr3l C as4c128m8d3l confidential 83 rev. 2 . 0 a ug . / 20 1 4 figure 6 8 . dynamic odt: behavior without write command, al = 0, cwl = 5 figure 69 . dynamic odt: behavior with odt pin being asserted together with write co mmand for a duration of 6 clock cycles v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d o n ' t c a r e t r a n s i t i o n i n g d a t a o d t o d t l o f f o d t l o n r t t d q t a o n ( m i n ) o d t h 4 t a o n ( m a x ) t a d c ( m i n ) t a d c ( m a x ) n o t e s : 1 . o d t h 4 i s d e f i n e d f r o m o d t r e g i s t e r e d h i g h t o o d t r e g i s t e r e d l o w , s o i n t h i s e x a m p l e , o d t h 4 i s s a t i s f i e d . 2 . o d t r e g i s t e r e d l o w a t t 5 w o u l d a l s o b e l e g a l . r t t _ n o m d q s , d q s # a d d r e s s c o m m a n d w r s 8 n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d o n ' t c a r e t r a n s i t i o n i n g d a t a o d t o d t l o f f o d t l c n w r t t d q t a o n ( m i n ) o d t h 8 t a d c ( m a x ) t a o f ( m i n ) t a o f ( m a x ) n o t e s : e x a m p l e f o r b l 8 ( v i a m r s o r o t f ) , a l = 0 , c w l = 5 . i n t h i s e x a m p l e , o d t h 8 = 6 i s e x a c t l y s a t i s f i e d . r t t _ w r v a l i d o d t l o n o d t l c w n 8 d i n b d i n b + 1 d i n b + 2 d i n b + 3 d q s , d q s # a d d r e s s c o m m a n d d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 w l
1gb ddr3l C as4c128m8d3l confidential 84 rev. 2 . 0 a ug . / 20 1 4 figure 70 . dynamic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example for bc4 (via mrs or otf), al = 0, cwl = 5. figure 71 . dynamic odt: behavior with odt pin being asserted together with write command for a duration of 4 clock cycles w r s 4 n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d o n ' t c a r e t r a n s i t i o n i n g d a t a o d t o d t l o f f o d t l c n w r t t d q t a o n ( m i n ) o d t h 4 t a d c ( m a x ) t a d c ( m i n ) t a d c ( m a x ) n o t e s : 1 . o d t h 4 i s d e f i n e d f r o m o d t r e g i s t e r e d h i g h t o o d t r e g i s t e r e d l o w , s o i n t h i s e x a m p l e , o d t h 4 i s s a t i s f i e d . t r a n s i t i o n i n g d o n v a l i d o d t l o n o d t l c w n 4 d i n n d i n n + 1 d i n n + 2 d i n n + 3 d q s , d q s # a d d r e s s c o m m a n d w l r t t _ w r t a o f ( m i n ) t a o f ( m a x ) r t t _ n o m w r s 4 n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k d o n ' t c a r e t r a n s i t i o n i n g d a t a o d t o d t l o f f o d t l c n w r t t d q t a o n ( m i n ) o d t h 4 t a d c ( m a x ) t a o f ( m i n ) t a o f ( m a x ) n o t e s : e x a m p l e f o r b c 4 ( v i a m r s o r o t f ) , a l = 0 , c w l = 5 . i n t h i s e x a m p l e , o d t h 4 = 4 i s e x a c t l y s a t i s f i e d . v a l i d o d t l o n o d t l c w n 4 d i n n d i n n + 1 d i n n + 2 d i n n + 3 d q s , d q s # a d d r e s s c o m m a n d w l r t t _ w r
1gb ddr3l C as4c128m8d3l confidential 85 rev. 2 . 0 a ug . / 20 1 4 figure 72 . asynchronous odt timings on ddr3l sdram with fast odt transition figure 73 . synchronous to asynchronous transition during precharge power down (with dll frozen) entry (al = 0; cwl = 5; tanpd = wl - 1 = 4) figure 74 . synchronous to asynchronous transition after refresh command (al = 0; cwl = 5; tanpd = wl - 1 = 4) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k t 1 2 t 1 3 t 1 4 d o n ' t c a r e t r a n s i t i o n i n g d a t a t 1 5 t 1 6 t 1 7 r t t t a o n p d ( m i n ) t a o n p d ( m a x ) t i h t i s t a o f p d ( m i n ) t a o f p d ( m a x ) c k e o d t t i h t i s r t t r e f n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k t 1 2 d o n ' t c a r e t r a n s i t i o n i n g d a t a r t t t r f c ( m i n ) t c p d e d ( m i n ) c k e t a o f ( m i n ) t a o f ( m a x ) r t t o d t l o f f t a o f p d ( m i n ) r t t o d t l o f f + t a o f p d ( m a x ) o d t l o f f + t a o f p d ( m i n ) t a o f p d ( m a x ) t a o f p d ( m i n ) p d e n t r y t r a n s i t i o n p e r i o d t a o f p d ( m a x ) r t t t 1 3 t a 0 t a 1 t a 2 t a 3 t a n p d r t t r t t c o m m a n d l a s t s y n c . o d t s y n c . o r a s y n c . o d t f i r s t a s y n c . o d t t i m e b r e a k r e f n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k t 1 2 d o n ' t c a r e t r a n s i t i o n i n g d a t a r t t t r f c ( m i n ) t c p d e d ( m i n ) c k e t a o f ( m i n ) t a o f ( m a x ) r t t o d t l o f f t a o f p d ( m i n ) r t t o d t l o f f + t a o f p d ( m a x ) o d t l o f f + t a o f p d ( m i n ) t a o f p d ( m a x ) t a o f p d ( m i n ) p d e n t r y t r a n s i t i o n p e r i o d t a o f p d ( m a x ) r t t t 1 3 t a 0 t a 1 t a 2 t a 3 t a n p d r t t r t t c o m m a n d l a s t s y n c . o d t s y n c . o r a s y n c . o d t f i r s t a s y n c . o d t t i m e b r e a k
1gb ddr3l C as4c128m8d3l confidential 86 rev. 2 . 0 a ug . / 20 1 4 figure 75 . asynchronous to synchronous transition during precharge power down ( with dll frozen) exit (cl = 6; al = cl - 1; cwl = 5; ta npd = wl - 1 = 9) figure 76 . transition period for short cke cycles, entry and exit period overlapping (al = 0, wl = 5, tanpd = wl - 1 = 4) n o p n o p n o p n o p n o p n o p n o p n o p n o p t 0 t 1 t 2 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 t a 6 t b 0 t b 1 c k # c k t b 2 d o n ' t c a r e t r a n s i t i o n i n g d a t a r t t t x p d l l t a n p d c k e t a o f p d ( m i n ) t a o f p d ( m a x ) t a o f p d ( m i n ) r t t o d t l o f f + t a o f ( m a x ) o d t l o f f + t a o f ( m i n ) t a o f p d ( m a x ) t a o f ( m i n ) p d e x i t t r a n s i t i o n p e r i o d t a o f ( m a x ) r t t t c 0 t c 1 t c 2 t d 0 t d 1 r t t r t t r t t o d t l o f f t i m e b r e a k n o p n o p n o p n o p n o p c o m m a n d l a s t a s y n c . o d t s y n c . o r a s y n c . o d t f i r s t s y n c . o d t t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k t 1 2 t a n p d d o n ' t c a r e c k e t 1 3 t 1 4 c k e p d e x i t t r a n s i t i o n p e r i o d n o p r e f n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t r f c ( m i n ) p d e n t r y t r a n s i t i o n p e r i o d t a n p d t x p d l l s h o r t c k e l o w t r a n s i t i o n p e r i o d c o m m a n d t a n p d s h o r t c k e h i g h t r a n s i t i o n p e r i o d t x p d l l t i m e b r e a k
1gb ddr3l as4c128m8d3l confidential 87 rev. 2.0 a ug . / 20 14 figure 77. 78 -ball bga package 8 x1 0.5x1.2mm(max) outline drawing information symbol dimension in inch dimension in mm min nom max min nom max a -- -- 0.047 -- -- 1.20 a1 0.012 -- 0.016 0.25 -- 0.40 d 0.311 0.315 0.319 7.90 8.00 8.10 e 0.409 0.413 0.417 10.40 10.50 10.60 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.378 -- -- 9.60 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50
1gb ddr3l as4c128m8d3l confidential 88 rev. 2.0 a ug . / 20 14 part numbering system alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650- 610- 6800 fax: 650- 620- 9211 www.alliancememory.com copyright ? alliance memory all rights reserved ? copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 alliance memory inc. reserves the right to change products or specification without notice. as4c 128m8d3l 12 b c/i n dram 128m8=128mx8 d3l=lpddr3 12=800mhz b = fbga c=commercial (0 c 95 c) i=industrial (- 40 c 95 c) indicates pb and halogen free

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